EGLXT973QEA3V Intel, EGLXT973QEA3V Datasheet - Page 12

• Manufacturer Part Number: EGLXT973QEA3V
• Manufacturer: Intel

Specifications of EGLXT973QEA3V

• Lead Free Status / RoHS Status: Compliant

LXT973 PHY Transceiver
Specification Update
249737, Revision 10.0
20 March 2007
Item 7:
Problem
Implication
Workaround Clear Register bit 16.8 so that the proper clock is used. This bit is set on power-up.
Status
Item 8:
Problem
Implication
Workaround Write Register bits 4.9:5 immediately before the start of a new auto-negotiation process.
Status
Item 9:
Problem
Implication
Workaround Use the MAC layer protocol to detect corrupt symbols in the packet.
Status
Cortina Systems
Internal Loopback Receive Disable
The recovered clock from the receive data is used instead of the transmit clock when
setting a port to 10 Mbps internal loopback mode.
When the port is connected to a link partner transmitting data or idle signals, the loopback
data is corrupted because the receiver data recovered clock is used to capture the
loopback data.
There are no plans to fix this erratum.
Changing Advertised Duplex While Link Is Up
Writing to Register bits 4.9:5, which control duplex mode advertisement while link is up
and auto-negotiation is enabled, immediately changes the PHY mode of operation to the
new duplex mode. When written, the values in this register are not intended to affect PHY
operation until a new auto-negotiation cycle is completed.
A possible mixed-duplex operation will exist during the time between Register bits 4.9:5
writes and the start of a new auto-negotiation process.
There are no plans to fix this erratum.
Detection of Illegal Symbols After SSD
An illegal symbol placed immediately after the Start-of-Stream Delimiter (SSD) (preamble
after JK) is not detected. However, any subsequent corrupt symbol will be detected.
Standard Frame Contents:
RXER will not assert if this symbol location is corrupted. However, an error in this location
does not affect packet integrity.
There are no plans to fix this erratum.
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Location of Symbol
SSD
/J/K/5/5/5/5/5/5/5/5/5/5/5/5/5/5/5/D/destination address, source address, . . . CRC/T/R/
SSD – Start-of-Stream Delimiter
SOF – Start-of-Frame Delimiter
ESD – End-of-Stream Delimiter
Preamble
SOF
5.0 Errata
Page 12
ESD