PEB3265F-V1.5 Infineon Technologies, PEB3265F-V1.5 Datasheet - Page 298
PEB3265F-V1.5
Manufacturer Part Number
PEB3265F-V1.5
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB3265F-V1.5.pdf
(383 pages)
Specifications of PEB3265F-V1.5
Lead Free Status / RoHS Status
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Preliminary
Bit
OFFSET-L[7:0]
Bit
R1-HW
R1-TS[6:0]
Data Sheet
20
21
H
H
OFR2
PCMR1
7
HW
R1-
7
Selection of the PCM highway for receiving PCM data or the higher byte
of the first data sample if linear 16 kHz PCM mode is selected.
R1-HW = 0
R1-HW = 1
Selection of the PCM time slot used for data reception.
Note: The programmed PCM time slot must correspond to the available
6
Offset register low byte.
The value of this register together with OFFSET-H is added to the
input of the DC loop to compensate a given offset of the current
sensors in the SLIC-S/-S2.
slots defined by the PCLK frequency. No reception will occur if a
slot outside the actual numbers of slots is programmed. In linear
mode (bit LIN = 1 in register BCR3) R1-TS defines the first of two
consecutive slots used for reception.
6
Offset Register 2 (Low Byte)
PCM Receive Register 1
5
5
PCM highway A is selected.
PCM highway B is selected.
SLICOFI-2x Command Structure and Programming
4
OFFSET-L[7:0]
4
298
R1-TS[6:0]
3
3
2
2
00
00
1
H
H
DuSLIC-S/-S2
1
2000-07-14
0
0
Y
Y
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