PEB4265TV12NT Infineon Technologies, PEB4265TV12NT Datasheet - Page 139
PEB4265TV12NT
Manufacturer Part Number
PEB4265TV12NT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB4265TV12NT.pdf
(383 pages)
Specifications of PEB4265TV12NT
On-hook Transmission
Yes
Polarity Reversal
Yes
On-chip Ring Relay Driver
Yes
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Pin Count
22
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Preliminary
clock rate is twice the data rate), the first rising edge indicates the start of a bit, while, by
default, the second falling edge is used to buffer the contents of the data line DRA (DRB).
Figure 58
The data rate of the interface can vary from 2*128 kbit/s to 2*8192 kbit/s (two highways).
A frame may consist of up to 128 time slots of 8 bits each. The time slot and PCM
Data Sheet
FSC
DRA
DXA
TCA
PCLK
DETAIL A:
Time Slot
General PCM Interface Timing
0 1 2
FSC
DRA
DXA
TCA
PCLK
Detail A
3
High 'Z'
Clock
Bit
High 'Z'
7
0 1
6
5
2 3 4 5 6
139
Voice
Voice
Data
Data
4
3
2
125 µs
1
0
7
High 'Z'
High 'Z'
Time Slot
ezm14046.wmf
31
Interfaces
2000-07-14
DuSLIC
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