SI3215-C-GMR Silicon Laboratories Inc, SI3215-C-GMR Datasheet - Page 15

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SI3215-C-GMR

Manufacturer Part Number
SI3215-C-GMR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI3215-C-GMR

Lead Free Status / RoHS Status
Compliant
Table 11. Switching Characteristics—PCM Highway Serial Interface
V
Parameter
PCLK Frequency
PCLK Duty Cycle Tolerance
PCLK Period Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX
Transition
Delay Time, PCLK Rise to DTX Tri-State
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
Notes:
D
= 3.13 to 5.25 V, T
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
SCLK
SDO
SDI
CS
A
= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C
t
su1
t
d1
t
r
2
Figure 7. SPI Timing Diagram
Symbol
t
1/t
t
t
t
jitter
t
t
t
t
t
su1
su2
dty
t
d1
d2
d3
h1
h2
t
r
f
c
Rev. 0.92
t
su2
t
t
c
thru
Conditions
t
d2
t
Test
h2
L
= 20 pF
Min
–120
40
25
20
25
20
1
IH –
V
t
r
I/O –
t
h1
Typ
0.256
0.512
0.768
1.024
1.536
2.048
4.096
8.192
50
0.4 V, V
1
t
cs
IL
t
d3
= 0.4 V
Max
120
60
25
25
20
20
20
Si3215
1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
15

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