HC55121IM Intersil, HC55121IM Datasheet - Page 20

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HC55121IM

Manufacturer Part Number
HC55121IM
Description
Manufacturer
Intersil
Datasheet

Specifications of HC55121IM

Number Of Channels
1
On-hook Transmission
Yes
Polarity Reversal
Yes
On-chip Ring Relay Driver
Yes
Longitudinal Balanced
53
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
PLCC
Loop Current Limit
30mA
Operating Temperature Classification
Industrial
Pin Count
28
Mounting
Surface Mount
Operating Current
2.7mA
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HC55121IMZ
Manufacturer:
Intersil
Quantity:
10 000
SPM Pin
For optimum performance, the PC board interconnect the
SPM pin should be as short as possible. If pulses metering is
not being used, then this pin should be grounded as close to
the device pin as possible.
RLIM Pin
The current limiting resistor R
RLIM pin as possible.
Digital Logic Inputs
Table 1 is the logic truth table for the 3V to 5V logic input
pins. A combination of the control pins C3, C2 and C1 select
1 of the possible 6 operating states. The 8th state listed is
Thermal Shutdown. Thermal Shutdown protection is invoked
if a fault condition on the tip or ring causes the junction
temperature of the die to exceed 175°C. A description of
each operating state and the control logic follows:
Open Circuit State (C3 = 0, C2 = 0, C1 = 0)
In this state, the tip and ring outputs are in a high impedance
condition (>1MΩ). No supervisory functions are available
and SHD and GKD outputs are at a TTL high level.
4-wire loopback testing can be performed in this state. With
the PTG pin floating, the signal on the V
of phase and approximately 2 times the V
STATE
0
1
2
3
4
5
6
7
8
C3
X
0
0
0
0
1
1
1
1
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
C2
X
0
0
1
1
0
0
1
1
C1
X
0
1
0
1
0
1
0
1
20
LIM
needs to be as close to the
Open Circuit State
Ringing State
(Previous State cannot be Reverse
Active State)
Forward Active State
Test Active State
Requires previous state to be in the
Forward Active state to determine the
On hook or Off hook status of the line.
Tip Open - Ground Start State
Reserved
Reverse Active State
Test Reversal Active State
Requires previous state to be in the
Reverse Active state to determine the
On hook or Off hook status of the line.
Thermal Shutdown
SLIC OPERATING STATE
TX
RX
output is 180
input signal. If
TABLE 1. DETECTOR STATES
o
out
4 wire loopback test capability
Ring Trip Detector
Loop Current Detector
Ground Key Detector
On Hook Loopback Detector
Ground Key Detector
Off Hook Loop Current Detector
Line Voltage Detector
Ground Key Detector
Reserved
Loop Current Detector
Ground Key Detector
On Hook Loop Current Detector
Off Hook Loop Current Detector
Line Voltage Detector
Layout of the 2-Wire Impedance Matching
Resistor Z
Proper connection to the ZT pin is to have the external Z
network as close to the device pin as possible.
The ZT pin is a high impedance pin that is used to set the
proper feedback for matching the impedance of the 2-wire
side. This will eliminate circuit board capacitance on this pin
to maintain the 2-wire return loss across frequency.
the PTG pin is grounded, then the amplitude will be
approximately the same as its input and 180
Ringing State (C3 = 0, C2 = 0, C1 = 1)
In this state, the output of the ring relay driver pin (RRLY)
goes low (energizing the ring relay to connect the ringing
signal to the phone) if either of the following two conditions
are satisfied:
(1) The RSYNC_REV pin is grounded through a resistor -
This connection enables the RRLY pin to go low the instant
the ringing state is invoked, without any regard for the
ringing voltage (90V
contacts. The resistor (34.8kΩ to 70kΩ) is required to limit
the current into the RSYNC_REV pin.
(2) A ring sync pulse is applied to the RSYNC_REV pin -
This connection enables the RRLY pin to go low at the
command of a ring sync pulse. A ring sync pulse should go
ACTIVE DETECTOR
T
RMS
-120V
RMS
) across the relay
HIGH
LOW
LOW
LOW
LOW
SHD
N/A
OUTPUT
o
out of phase.
GKD_ LVM
HIGH
HIGH
HIGH
HIGH
LOW
June 1, 2006
N/A
FN4659.13
T

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