HC5503CBZ Intersil, HC5503CBZ Datasheet - Page 11

• Manufacturer Part Number: HC5503CBZ
• Manufacturer: Intersil

Specifications of HC5503CBZ

• Number Of Channels: 1
• On-hook Transmission: Yes
• Polarity Reversal: No
• On-chip Ring Relay Driver: Yes
• Longitudinal Balanced: 58
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Loop Current Limit: 30mA
• Operating Temperature Classification: Commercial
• Pin Count: 24
• Mounting: Surface Mount
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Lead Free Status / RoHS Status: Compliant

is the calculated value of 0.633 plus the feedback which is
1/4 T
The voltage at R
Substituting the values for T
setting them equal to each other, the values of R3 and R
can then be determined.
Setting the value of R
200kΩ .
Notice that the input voltage for the incoming signal (I
taken at R
CODEC (point A, Figure 6). This alternative method is used
because the tolerance effects of R
balance are eliminated.
Power Denial (PD)
Power denial limits power to the subscriber loop: it does not
power down the SLIC, i.e., the SLIC will still consume its
normal on-hook quiescent power during a power denial
period. This function is intended to “isolate” from the battery,
under processor control, selected subscriber loops during an
overload or similar fault status.
If PD is selected, the logic circuitry inhibits RC and switches in
a current source to C
-3.5V at which point it is clamped. Since tip feed is always at
-4V, the battery feed across the loop is essentially zero, and
minimum loop power will be dissipated if the circuit goes off-
hook. No signaling functions are available during this mode.
After power denial is released (PD = 1), it will be several
hundred milliseconds (300ms) before the V
reaches its nominal battery setting. This is due to the RC
time constant of R
R
0.633
-------------- -
R
X
4
=
X
0.633
=
(for matching to a 600Ω load, reference Equation 8).
0.474
-------------- -
R
X
3
–
, instead of the conventional method at the
R
FIGURE 6. TRANSHYBRID CIRCUIT
1
-- - 0.633
4
T
150kΩ
X
X
(
x
I
1
is calculated in Equation 25.
21
1
)
and C
3
. The capacitor charges up to a nominal
=
R
to 150kΩ sets the value of R
3
0.474
1
X
I
R
.
2
11
4
and R
200kΩ
R
1
2
R
X
on the transhybrid
1
into Equation 24 and
R
5
V
IN
RF
+
-
CODEC/
+
output
-
FILTER
A
4
(EQ. 25)
(EQ. 26)
1
to be
) is
V
0
+
-
4
HC5503
The Logic Network
The logic network utilizes I
outputs are LS TTL compatible: the relay driver is an open
collector output that can sink 60mA with a V
Figure 9 is a schematic of the combination logic within the
network. The external inputs RC (Relay Control) and PD
(Power Denial) allow the switch controller to ring the line or
deny power to the loop, respectively. The Ring
Synchronization input (RS) facilitates switching of the ring
relay near a ring current zero crossing in order to minimize
inductive kickback from the telephone ringer.
Line Fault Protection
The subscriber loop can exist in a very hostile electrical
environment. It is often in close proximity to very high
voltage power lines, and can be subjected to lightning
induced voltage surges. The SLIC has to provide isolation
between the subscriber loop and the PBX/Key telephone
system.
The most stringent line fault condition that the SLIC has to
withstand is that of the lightning induced surge.
The Intersil monolithic SLIC, in conjunction with a simple low
cost diode bridge, can achieve up to 450V of isolation
between the loop and switch. The level of isolation is a
function of the packaging technology and geometry together
with the chip layout geometries. One of the principal reasons
for using DI technology for fabricating the SLIC is that it
lends itself most readily to manufacturing monolithic circuits
for high voltage applications.
Figures 10 shows the application circuit for the HC5503. A
secondary protection diode bridge is indicated which
protects the feed amplifiers during a fault. Most line systems
will have primary protection networks. They often take the
form of a carbon block or arc discharge device. These limit
the fault voltage to less than 450V peak before it reaches the
line cards. Thus when a transient high voltage fault has
occurred, it will be transmitted as a wave front down the line.
The primary protection network must limit the voltage to
less than 450V. The attenuated wave front will continue
down the line towards the SLIC. The feed amplifier outputs
appear to the surge as very low impedance paths to the
system battery. Once the surge reaches the feed resistors,
fault current will flow into or out of the feed amplifier output
stages until the relevant protection diodes switch on. Once
the necessary diodes have started to conduct all the fault
current will be handled by them.
If the user wishes to characterize SLIC devices under
simulated high voltage fault conditions on the bench, he should
ensure that the negative battery power supply has sufficient
current capability to source the negative peak fault current and
low series inductance. If this is not the case, then the battery
supply could be pulled more negative and destroy the SLIC if
the total (V
CC
+ V
BAT
) voltage across it exceeds 75V.
2
L logic. All external inputs and
CE
of 1V.