XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 102

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 3: Phase-Locked Loops (PLLs)
102
Counter Control
The PLL output counters provide a wide variety of synthesized clock using a combination
of DIVIDE, DUTY_CYCLE, and PHASE.
impact the counter output.
The top waveform represents either the output from the VCO in PLL mode.
X-Ref Target - Figure 3-6
DUTY_CYCLE = 0.75
DUTY_CYCLE = 0.33
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
Counter Clock Input
PHASE = 180
PHASE = 180
PHASE = 360
DIVIDE = 2
PHASE = 0
DIVIDE = 2
DIVIDE = 2
DIVIDE = 1
PHASE = 0
DIVIDE = 1
DIVIDE = 3
PHASE = 0
DIVIDE = 3
PHASE = 0
(VCO)
Figure 3-6: Output Counter Clock Synthesis Examples
www.xilinx.com
Figure 3-6
illustrates how the counter settings
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_3_06_041406