XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 367

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

X-Ref Target - Figure 8-11
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
1001 0011
(Repeating
Pattern)
SERDES_MODE=MASTER
BITSLIP_ENABLE = TRUE
BITSLIP_ENABLE = TRUE
D
D
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
Figure 8-11: Circuit Diagram for Bitslip Configuration in 1:8 SDR Mode
SHIFTIN1
ISERDES
ISERDES
(Master)
(Slave)
Figure 8-11
to TRUE. Two ISERDES modules are in a master-slave configuration for a data width of
eight.
Guidelines for Using the Bitslip Submodule
Set the BITSLIP_ENABLE attribute to TRUE. When BITSLIP_ENABLE is set to FALSE, the
Bitslip pin has no effect. In a master-slave configuration, the BITSLIP_ENABLE attribute in
both modules must be set to TRUE.
To invoke a Bitslip operation, the BITSLIP port must be asserted High for one CLKDIV
cycle. In SDR mode, Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip
must be deasserted for at least one CLKDIV cycle between two Bitslip assertions. In both
SDR and DDR mode, the total latency from when the ISERDES captures the asserted
Bitslip input to when the “bit-slipped” ISERDES outputs Q1–Q6 are sampled into the
FPGA logic by CLKDIV is two CLKDIV cycles.
IOB
SHIFTIN2
(Q7)Q3
(Q8)Q4
BITSLIP
BITSLIP
illustrates the ISERDES configured in 1:8 SDR mode with Bitslip_ENABLE set
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q5
Q6
Initial
www.xilinx.com
1
0
0
1
0
0
1
1
Bitslip
1st
1
1
0
0
1
0
0
1
Input Serial-to-Parallel Logic Resources (ISERDES)
Bitslip
2nd
1
1
1
0
0
1
0
0
Bitslip
3th
0
1
1
1
0
0
1
0
Bitslip
4th
0
0
1
1
1
0
0
1
Bitslip
5th
1
0
0
1
1
1
0
0
Bitslip
Bitslip signal from system
6th
0
1
0
0
1
1
1
0
Bitslip
7th
0
0
1
0
0
1
1
1
8th Bitslip
(Back to initial)
1
0
0
1
0
0
1
1
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