XC6SLX25T-2FGG484I Xilinx Inc, XC6SLX25T-2FGG484I Datasheet - Page 43
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XC6SLX25T-2FGG484I
Manufacturer Part Number
XC6SLX25T-2FGG484I
Description
FPGA, SPARTAN-6 LXT, 24K, 484FGGBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXTr
Specifications of XC6SLX25T-2FGG484I
No. Of Logic Blocks
3758
No. Of Macrocells
24051
Family Type
Spartan-6
No. Of Speed Grades
2
Total Ram Bits
958464
No. Of I/o's
250
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Number Of Logic Elements/cells
24051
Number Of Labs/clbs
1879
Number Of I /o
250
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Package
484FBGA
Family Name
Spartan®-6
Device Logic Cells
24051
Device Logic Units
15000
Number Of Registers
30064
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
958464
Core Supply Voltage Range
1.14V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX25T-2FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC6SLX25T-2FGG484I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DSP48A1 Switching Characteristics
Table 43: DSP48A1 Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T
T
T
T
T
T
T
T
T
T
T
T
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T
T
T
T
T
T
T
T
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T
T
T
T
T
T
T
T
T
T
DSPDCK_A_A1REG
DSPCKD_A_A1REG
DSPDCK_D_B1REG
DSPCKD_D_B1REG
DSPDCK_C_CREG
DSPCKD_C_CREG
DSPDCK_D_DREG
DSPCKD_D_DREG
DSPDCK_OPMODE_B1REG
DSPCKD_OPMODE_B1REG
DSPDCK_OPMODE_OPMODEREG
DSPCKD_OPMODE_OPMODEREG
DSPDCK_A_MREG
DSPCKD_A_MREG
DSPDCK_B_MREG
DSPCKD_B_MREG
DSPDCK_D_MREG
DSPCKD_D_MREG
DSPDCK_OPMODE_MREG
DSPCKD_OPMODE_MREG
DSPDCK_A_PREG
DSPCKD_A_PREG
DSPDCK_B_PREG
DSPCKD_B_PREG
DSPDCK_C_PREG
DSPCKD_C_PREG
DSPDCK_D_PREG
DSPCKD_D_PREG
DSPDCK_OPMODE_PREG
DSPCKD_OPMODE_PREG
Symbol
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
A input to A1 register CLK
D input to B1 register CLK
C input to C register CLK
D input to D register CLK
OPMODE input to B1 register CLK
OPMODE input to OPMODE
register CLK
A input to M register CLK
B input to M register CLK
D input to M register CLK
OPMODE to M register CLK
A input to P register CLK
B input to P register CLK
C input to P register CLK
D input to P register CLK
OPMODE input to P register CLK
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
adder
Pre-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Multiplier
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
adder
Post-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–0.07
–0.40
–0.68
–0.56
–0.48
–0.48
–0.76
–0.59
–0.93
–0.23
–0.92
–0.84
–0.87
–0.22
0.15
0.09
1.90
0.11
0.15
0.09
0.15
1.97
0.01
0.18
0.12
3.06
3.96
4.23
4.18
2.37
4.32
5.87
4.14
2.20
5.90
6.21
1.69
2.09
-3
Speed Grade
–0.07
–0.40
–0.68
–0.56
–0.48
–0.48
–0.76
–0.59
–0.93
–0.23
–0.92
–0.84
–0.87
–0.22
0.17
0.09
1.95
0.13
0.15
0.10
0.15
2.00
0.01
0.21
0.12
3.51
4.58
4.80
4.80
2.70
5.06
6.87
4.68
2.25
6.91
7.27
1.98
2.30
-3N
–0.07
–0.40
–0.68
–0.56
–0.48
–0.48
–0.76
–0.59
–0.93
–0.23
–0.92
–0.84
–0.87
–0.22
0.17
0.09
1.95
0.13
0.15
0.10
0.15
2.00
0.01
0.21
0.12
3.51
4.58
4.80
4.80
2.70
5.06
6.87
4.68
2.25
6.91
7.27
1.98
2.30
-2
–0.07
–0.40
–0.68
–0.56
–0.48
–0.48
–0.76
10.55
–0.59
–0.93
–0.23
10.39
–0.92
10.43
–0.84
–0.87
–0.22
0.32
0.09
2.82
0.24
0.09
0.19
0.12
2.85
0.01
0.40
0.12
3.97
7.00
6.84
6.88
4.28
7.52
8.12
3.27
3.62
3.79
-1L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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