XC6SLX25T-2FGG484I Xilinx Inc, XC6SLX25T-2FGG484I Datasheet - Page 65
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XC6SLX25T-2FGG484I
Manufacturer Part Number
XC6SLX25T-2FGG484I
Description
FPGA, SPARTAN-6 LXT, 24K, 484FGGBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXTr
Specifications of XC6SLX25T-2FGG484I
No. Of Logic Blocks
3758
No. Of Macrocells
24051
Family Type
Spartan-6
No. Of Speed Grades
2
Total Ram Bits
958464
No. Of I/o's
250
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Number Of Logic Elements/cells
24051
Number Of Labs/clbs
1879
Number Of I /o
250
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Package
484FBGA
Family Name
Spartan®-6
Device Logic Cells
24051
Device Logic Units
15000
Number Of Registers
30064
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
958464
Core Supply Voltage Range
1.14V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX25T-2FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC6SLX25T-2FGG484I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 71: Global Clock Setup and Hold With PLL in System-Synchronous Mode
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
PSPLL
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
IFF = Input Flip-Flop or Latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Symbol
/ T
PHPLL
No Delay Global Clock and IFF
System-Synchronous Mode
Description
(2)
with PLL in
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
Device
–0.03
1.37/
1.37/
1.33/
1.65/
1.70/
1.55/
1.57/
1.77/
1.80/
1.44/
1.51/
1.39/
1.41/
0.25
0.21
0.28
0.28
0.18
0.18
0.21
0.21
0.32
0.32
0.49
0.49
-3
(1)
–0.02
1.48/
1.53/
1.71/
1.71/
1.64/
1.64/
1.89/
1.89/
1.52/
1.52/
1.48/
1.48/
0.21
0.28
0.28
0.18
0.18
0.21
0.21
0.32
0.32
0.49
0.49
Speed Grade
N/A
-3N
–0.02
1.52/
1.52/
1.60/
1.91/
1.91/
1.75/
1.75/
2.13/
2.13/
1.70/
1.70/
1.67/
1.67/
0.41
0.26
0.28
0.28
0.18
0.18
0.21
0.21
0.32
0.32
0.49
0.49
-2
2.07/
2.07/
1.57/
2.44/
2.02/
2.46/
1.78/
1.94/
0.69
0.69
0.48
0.76
0.90
0.53
0.86
0.94
N/A
N/A
N/A
N/A
N/A
-1L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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