MCP4706A3T-E/MAY Microchip Technology, MCP4706A3T-E/MAY Datasheet - Page 10
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MCP4706A3T-E/MAY
Manufacturer Part Number
MCP4706A3T-E/MAY
Description
Single, 8-bit NV DAC With Ext Vref And I2C Interface 6 DFN 2x2x0.9mm T/R
Manufacturer
Microchip Technology
Series
-r
Datasheet
1.MCP4706A0T-ECH.pdf
(86 pages)
Specifications of MCP4706A3T-E/MAY
Settling Time
6µs
Number Of Bits
8
Data Interface
EEPROM, I²C, Serial
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
1.10W
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
6-VDFN Exposed Pad
Number Of Outputs And Type
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
MCP4706/4716/4726
FIGURE 1-4:
TABLE 1-3:
DS22272A-page 10
I
Note 1:
2
Param.
C AC Characteristics
No.
100
101
2:
3:
4:
5:
6:
7:
8:
SDA
Out
SDA
In
SCL
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I
requirement t
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
T
the SCL line is released.
The MCP47X6 device must provide a data hold time to bridge the undefined part between V
the falling edge of the SCL signal. This specification is not a part of the I
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
Use C
Not Tested. This parameter ensured by characterization.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
I
affected.
Ensured by the T
The specification is not part of the I 2 C specification. T
2
R
C bus line. If this parameter is too long, the Data Input Setup (T
T
T
Sym
max.+t
HIGH
LOW
b
I
2
in pF for the calculations.
C BUS DATA REQUIREMENTS (SLAVE MODE)
Data Input: This parameter must be longer than t
Data Output: This parameter is characterized, and tested indirectly by testing T
SU;DAT
I
Characteristic
90
2
Clock high time
Clock low time
C Bus Data Timing.
SU;DAT
103
91
AA
= 1000 + 250 = 1250 ns (according to the standard-mode I
3.4 MHz specification test.
≥ 250 ns must then be met. This will automatically be the case if the device does not
109
2
C-bus device can be used in a standard-mode (100 kHz) I
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
Operating Voltage V
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100
106
109
101
DD
4000
4700
1300
range is described in
Min
600
120
320
160
60
AA
107
= T
–40°C ≤ T
SP
HD:DAT
.
Max
—
—
—
—
—
—
SU:DAT
+ T
A
≤ +125°C (Extended)
FSDA
2
Units
) or Clock Low time (T
C specification, but must be tested
ns
ns
ns
ns
ns
ns
ns
ns
Electrical characteristics
© 2011 Microchip Technology Inc.
2
(or T
C bus specification) before
92
2.7V-5.5V
2.7V-5.5V
4.5V-5.5V
4.5V-5.5V
2.7V-5.5V
2.7V-5.5V
4.5V-5.5V
4.5V-5.5V
102
RSDA
2
C-bus system, but the
110
).
Conditions
AA
IH
parameter.
LOW
and V
) can be
IL
of