MCP4706A3T-E/MAY Microchip Technology, MCP4706A3T-E/MAY Datasheet - Page 8
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MCP4706A3T-E/MAY
Manufacturer Part Number
MCP4706A3T-E/MAY
Description
Single, 8-bit NV DAC With Ext Vref And I2C Interface 6 DFN 2x2x0.9mm T/R
Manufacturer
Microchip Technology
Series
-r
Datasheet
1.MCP4706A0T-ECH.pdf
(86 pages)
Specifications of MCP4706A3T-E/MAY
Settling Time
6µs
Number Of Bits
8
Data Interface
EEPROM, I²C, Serial
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
1.10W
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
6-VDFN Exposed Pad
Number Of Outputs And Type
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
MCP4706/4716/4726
1.1
FIGURE 1-1:
FIGURE 1-2:
TABLE 1-1:
DS22272A-page 8
Timing Characteristics
Power Up Reset
Delay
Brown Out Reset
Delay
Power Down Disable
Time Delay
Power Down Enable
Time Delay
SDA
SCL
V
V
SDA
SCL
V
OUT
DD
OUT
Parameters
I
2
C Mode Timing Waveforms and Requirements
V
IH
RESET TIMING
ACK
Power-On and Brown-Out Reset Waveforms.
I
2
C Power-Down Command Timing.
t
t
T
T
Sym
PORD
BORD
PDD
PDE
t
PDE
t
PORD
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
All parameters apply across the specified operating ranges unless noted.
V
Typical specifications represent values for V
DD
Stop
Min
—
—
—
—
—
= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
I
2
C Interface is operational
10.5
Typ
2.5
Start
60
1
5
Max
—
—
—
—
—
Units
µs
µs
µs
µs
µs
–40°C ≤ T
Monitor ACK bit response to ensure device
responds to command.
V
V
V
PD1:PD0 → ‘00’ (from ‘01’, ‘10’, or ‘11’),
from falling edge SCL at end of ACK bit.
V
PD1:PD0 → ‘00’ (from ‘01’, ‘10’, or ‘11’),
from falling edge SCL at end of ACK bit.
PD1:PD0 → ‘01’, ‘10’, or ‘11’ (from ‘00’),
from falling edge SCL at end of ACK bit.
DD
OUT
DD
DD
V
A
POR
t
BORD
transitions from V
= 5V
= 3V
≤ +125°C (extended)
driven to V
DD
(V
BOR
= 5.5V, T
)
© 2011 Microchip Technology Inc.
V
500 kΩ (typical) resistor
OUT
Conditions
OUT
pulled down by internal
A
ACK
disabled
= +25°C.
DD(MIN)
t
PDD
→ > V
V
IH
POR