OP496GS-REEL Analog Devices Inc, OP496GS-REEL Datasheet - Page 12

• Manufacturer Part Number: OP496GS-REEL
• Description: IC,Operational Amplifier,QUAD,BICMOS,SOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of OP496GS-REEL

• Rohs Status: RoHS non-compliant
• Amplifier Type: General Purpose
• Number Of Circuits: 4
• Output Type: Rail-to-Rail
• Slew Rate: 0.3 V/µs
• Gain Bandwidth Product: 450kHz
• Current - Input Bias: 10nA
• Voltage - Input Offset: 35µV
• Current - Supply: 60µA
• Current - Output / Channel: 4mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12 V, ±1.5 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• -3db Bandwidth: -

OP196/OP296/OP496
APPLICATIONS INFORMATION
Functional Description
The OP196 family of operational amplifiers is comprised of single-
supply, micropower, rail-to-rail input and output amplifiers. Input
offset voltage (V
will deliver ±5 mA to a load. Supply current is only 50 µA, while
bandwidth is over 450 kHz and slew rate is 0.3 V/µs. TPC 36 is
a simplified schematic of the OP196—it displays the novel cir-
cuit design techniques used to achieve this performance.
Input Overvoltage Protection
The OPx96 family of op amps uses a composite PNP/NPN
input stage. Transistor Q1 in Figure 36 has a collector-base
voltage of 0 V if +IN = V
tion will be forward biased and large diode currents will flow,
which may damage the device. The same situation applies to
+IN on the base of transistor Q5 being driven above V
fore, the inverting and noninverting inputs must not be driven
above or below either supply rail unless the input current is
limited.
Figure 1 shows the input characteristics for the OPx96 family.
This photograph was generated with the power supply pins
connected to ground and a curve tracer’s collector output drive
connected to the input. As shown in the figure, when the input
voltage exceeds either supply by more than 0.6 V, internal
pn-junctions energize and permit current flow from the inputs
to the supplies. If the current is not limited, the amplifier may
be damaged. To prevent damage, the input current should be
limited to no more than 5 mA.
Output Phase Reversal
Some other operational amplifiers designed for single-supply
operation exhibit an output voltage phase reversal when their
inputs are driven beyond their useful common-mode range.
Typically for single-supply bipolar op amps, the negative supply
determines the lower limit of their common-mode range. With
these common-mode limited devices, external clamping diodes
are required to prevent input signal excursions from exceeding
the device’s negative supply rail (i.e., GND) and triggering
output phase reversal.
The OPx96 family of op amps is free from output phase reversal
effects due to its novel input structure. Figure 2 illustrates the
performance of the OPx96 op amps when the input is driven
beyond the supply rails. As previously mentioned, amplifier
input current must be limited if the inputs are driven beyond
–2
–4
–6
–8
8
6
4
2
0
OS
100
0%
90
10
) is only 300 µV maximum, while the output
–1.5 –1 –0.5 0
EE
INPUT VOLTAGE – V
. If +IN then exceeds V
0.5
1
1.5
EE
CC
, the junc-
. There-
the supply rails. In the circuit of Figure 2, the source ampli-
tude is ± 15 V, while the supply voltage is only ± 5 V. In this
case, a 2 kΩ source resistor limits the input current to 5 mA.
Input Offset Voltage Nulling
The OP196 provides two offset adjust terminals that can be
used to null the amplifier’s internal V
amplifier terminals should never be used to adjust system offset
voltages. A 100 kΩ potentiometer, connected as shown in Fig-
ure 3, is recommended to null the OP196’s offset voltage. Offset
nulling does not adversely affect TCV
that the trimming potentiometer temperature coefficient does
not exceed ± 100 ppm/°C.
Driving Capacitive Loads
OP196 family amplifiers are unconditionally stable with capaci-
tive loads less than 170 pF. When driving large capacitive loads
in unity-gain configurations, an in-the-loop compensation
technique is recommended, as illustrated in Figure 4.
V
R
IN
X
=
100
0%
90
10
R
O
R
R
F
R
G
G
C
5V
5V
F
WHERE R
=
I +
OP296
R
(
F
|A
TIME – 1ns/DIV
2
3
O
I
CL
OP196
C
= OPEN-LOOP OUTPUT RESISTANCE
1
F
|
) (
V+
7
5
R
100k
F
R
V
A
R
+ R
4
S
V
X
F
OS
=
= 1
OS
G
6
V–
1ms
. In general, operational
)
5V
performance, providing
C
L
R
O
C
L
0
0
V
V
V
IN
OUT
OUT
D