PIC12F1822T-I/SN Microchip Technology, PIC12F1822T-I/SN Datasheet - Page 167
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PIC12F1822T-I/SN
Manufacturer Part Number
PIC12F1822T-I/SN
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Specifications of PIC12F1822T-I/SN
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.3
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
See
more information.
19.4
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 21.6 “Timer1 Gate”
This feature is useful for timing the duration or interval
of an analog event.
It is recommended that the comparator output be syn-
chronized to Timer1. This ensures that Timer1 does not
increment while a change in the comparator is occur-
ring.
19.4.1
The output from either comparator, C1 or C2, can be
synchronized with Timer1 by setting the CxSYNC bit of
the CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagrams (Figures
Timer1
information.
2010 Microchip Technology Inc.
Section 30.0 “Electrical Specifications”
Comparator Hysteresis
Timer1 Gate Operation
Block
COMPARATOR OUTPUT
SYNCHRONIZATION
Diagram
19-2
(Figure
for more information.
and 19-3) and the
21-1)
PIC12F/LF1822/PIC16F/LF1823
for
more
Preliminary
for
19.5
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a Falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
• CxINTN bit of the CMxCON1 register (for a falling
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
19.6
Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• C1IN+ or C2IN+ analog pin
• DAC
• FVR (Fixed Voltage Reference)
• V
See
for more information on the Fixed Voltage Reference
module.
See
(DAC) Module”
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
register
edge detection)
edge detection)
Note:
SS
Section 14.0 “Fixed Voltage Reference (FVR)”
Section 17.0 “Digital-to-Analog
(Ground)
Comparator Interrupt
Comparator Positive Input
Selection
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
for more information on the DAC input
DS41413B-page 167
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