PIC12F1822T-I/SN Microchip Technology, PIC12F1822T-I/SN Datasheet - Page 232

• Manufacturer Part Number: PIC12F1822T-I/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822T-I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
The I
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 25-2
ule in Master mode.
interface module in Slave mode.
FIGURE 25-2:
DS41413B-page 232
2
C interface supports the following modes and
SDA
SCL
is a block diagram of the I
Figure 25-3
MSSP1 BLOCK DIAGRAM (I
SDA in
is a diagram of the I
Bus Collision
SCL in
2
C interface mod-
Read
MSb
Generate (SSP1CON2)
Address Match detect
Preliminary
Write collision detect
2
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock arbitration
C
Start bit detect,
Stop bit detect
Acknowledge
SSP1BUF
SSP1SR
2
C™ MASTER MODE)
LSb
Write
Clock
Shift
data bus
Internal
Set/Reset: S, P, SSP1STAT, WCOL, SSP1OV
Reset SEN, PEN (SSP1CON2)
Set SSP1IF, BCL1IF
 2010 Microchip Technology Inc.
[SSP1M 3:0]
Baud rate
generator
(SSP1ADD)