PIC16F1934-E/P Microchip Technology, PIC16F1934-E/P Datasheet - Page 253
![7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 PDIP .600in TUBE](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16F1934-E/P
Manufacturer Part Number
PIC16F1934-E/P
Description
7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 PDIP .600in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1936-ISS.pdf
(2 pages)
5.PIC16F1936-ISS.pdf
(10 pages)
6.PIC16F1936-ISS.pdf
(40 pages)
7.PIC16F1936-ISS.pdf
(30 pages)
8.PIC16F1936-ISS.pdf
(12 pages)
Specifications of PIC16F1934-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, MI2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
A/d Bit Size
10 bit
A/d Channels Available
14
Height
4.95 mm
Length
53.21 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
14.73 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1934-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1936-ISS PDF datasheet #4
- PIC16F1936-ISS PDF datasheet #5
- PIC16F1936-ISS PDF datasheet #6
- PIC16F1936-ISS PDF datasheet #7
- PIC16F1936-ISS PDF datasheet #8
- Current page: 253 of 508
- Download datasheet (5Mb)
23.5.2
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF reg-
ister and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF bit of the SSPSTAT
register is set, or bit SSPOV bit of the SSPCON1 reg-
ister is set. The BOEN bit of the SSPCON3 register
modifies this operation. For more information see
Register 23-4.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPIF, must be cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode. See Section 23.2.3 “SPI Master Mode”
for more detail.
23.5.2.1
This section describes a standard sequence of events
for the MSSP module configured as an I
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 23-13 and Figure 23-14 is used as a visual
reference for this description.
This is a step by step process of what typically must
be done to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Software clears SSPIF.
11. Software reads the received byte from SSPBUF
12. Steps 8-12 are repeated for all received bytes
13. Master sends Stop condition, setting P bit of
2009 Microchip Technology Inc.
Start bit detected.
S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDA low sending an ACK to the
master, and sets SSPIF bit.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
clearing the BF flag.
If SEN = 1; Slave software sets CKP bit to
release the SCL line.
The master clocks out a data byte.
Slave drives SDA low sending an ACK to the
master, and sets SSPIF bit.
clearing BF.
from the Master.
SSPSTAT, and the bus goes idle.
SLAVE RECEPTION
7-bit Addressing Reception
2
C communication.
2
C Slave in
Preliminary
23.5.2.2
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCL. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I
cation. Figure 23-15 displays a module using both
address and data holding. Figure 23-16 includes the
operation with the SEN bit of the SSPCON2 register
set.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPIF.
11. SSPIF set and CKP cleared after 8th falling
12. Slave looks at ACKTIM bit of SSPCON3 to
13. Slave reads the received data from SSPBUF
14. Steps 7-14 are the same for each received data
15. Communication is ended by either the slave
PIC16F193X/LF193X
Note: SSPIF is still set after the 9th falling edge of
S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
falling edge of SCL.
Slave clears the SSPIF.
Slave can look at the ACKTIM bit of the
SSPCON3 register to determine if the SSPIF
was after or before the ACK.
Slave reads the address value from SSPBUF,
clearing the BF flag.
Slave sets ACK value clocked out to the master
by setting ACKDT.
Slave releases the clock by setting CKP.
SSPIF is set after an ACK, not after a NACK.
If SEN = 1 the slave hardware will stretch the
clock after the ACK.
edge of SCL for a received data byte.
determine the source of the interrupt.
clearing BF.
byte.
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
SCL even if there is no clock stretching and
BF has been cleared. Only if NACK is sent to
Master is SSPIF not set
7-bit Reception with AHEN and
DHEN
DS41364D-page 253
2
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