PIC16F1934-E/P Microchip Technology, PIC16F1934-E/P Datasheet - Page 374
![7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 PDIP .600in TUBE](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16F1934-E/P
Manufacturer Part Number
PIC16F1934-E/P
Description
7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 PDIP .600in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1936-ISS.pdf
(2 pages)
5.PIC16F1936-ISS.pdf
(10 pages)
6.PIC16F1936-ISS.pdf
(40 pages)
7.PIC16F1936-ISS.pdf
(30 pages)
8.PIC16F1936-ISS.pdf
(12 pages)
Specifications of PIC16F1934-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, MI2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
A/d Bit Size
10 bit
A/d Channels Available
14
Height
4.95 mm
Length
53.21 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
14.73 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1934-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1936-ISS PDF datasheet #4
- PIC16F1936-ISS PDF datasheet #5
- PIC16F1936-ISS PDF datasheet #6
- PIC16F1936-ISS PDF datasheet #7
- PIC16F1936-ISS PDF datasheet #8
- Current page: 374 of 508
- Download datasheet (5Mb)
PIC16F193X/LF193X
MOVIW
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41364D-page 374
mm
00
01
10
11
Move literal to BSR
[ label ] MOVLB k
0 k 15
k BSR
None
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
Move INDFn to W
[ label ] MOVIW ++INDFn
[ label ] MOVIW --INDFn
[ label ] MOVIW INDFn++
[ label ] MOVIW INDFn--
[ label ] MOVIW k[INDFn]
[ label ] MOVIW INDFn
n [0,1]
mm [00, 01, 10, 11].
-32 k 31
If not present, k = 0.
INDFn W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
Z
Mode
Preincrement
Predecrement
Postincrement
Postdecrement
Syntax
++INDFn
--INDFn
INDFn++
INDFn--
Preliminary
MOVLP
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
Cycles:
Example:
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
Cycles:
Example:
Move literal to W
[ label ]
0 k 255
k (W)
None
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assem-
ble as ‘0’s.
1
1
After Instruction
Move literal to PCLATH
[ label ] MOVLP k
0 k 127
k PCLATH
None
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
Move W to f
[ label ]
0 f 127
(W) (f)
None
Move data from W register to register
‘f’.
1
1
Before Instruction
After Instruction
MOVLW
MOVWF
2009 Microchip Technology Inc.
MOVLW k
W
MOVWF
OPTION =
W
OPTION =
W
0x5A
OPTION
=
0x5A
=
=
f
0xFF
0x4F
0x4F
0x4F
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