PIC16F1938-E/MV Microchip Technology, PIC16F1938-E/MV Datasheet - Page 262
![28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V 28 UQFN 4x4x0.5mm TUBE](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC16F1938-E/MV
Manufacturer Part Number
PIC16F1938-E/MV
Description
28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1938-ISS.pdf
(10 pages)
Specifications of PIC16F1938-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1938-ISS PDF datasheet #4
- Current page: 262 of 508
- Download datasheet (5Mb)
PIC16F193X/LF193X
23.5.4
This section describes a standard sequence of events
for the MSSP module configured as an I
10-bit Addressing mode.
Figure 23-19 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPIF.
11. Slave reads the received matching address
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
14. If SEN bit of SSPCON2 is set, CKP is cleared by
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
17. If SEN is set the slave sets CKP to release the
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41364D-page 262
Note: Updates to the SSPADD register are not
Note: If the low address does not match, SSPIF
Bus starts Idle.
Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
Slave sends ACK and SSPIF is set.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
clearing the BF flag.
Slave loads low address into SSPADD,
releasing SCL.
Master sends matching low address byte to the
Slave; UA bit is set.
Slave sends ACK and SSPIF is set.
from SSPBUF clearing BF.
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
hardware and the clock is stretched.
clearing BF.
SCL.
allowed until after the ACK sequence.
and UA are still set so that the slave software
can set SSPADD back to the high address.
BF is not set because there is no match.
CKP is unaffected.
SLAVE MODE 10-BIT ADDRESS
RECEPTION
2
C communication.
2
C Slave in
Preliminary
23.5.5
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 23-20 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 23-21 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
10-BIT ADDRESSING WITH
ADDRESS OR DATA HOLD
2009 Microchip Technology Inc.
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