PIC16F506T-I/MG Microchip Technology, PIC16F506T-I/MG Datasheet - Page 54
![1.5 KB Flash, 67 RAM, 12 I/O, Comparator, 8bit ADC 16 QFN 3x3x0.9mm T/R](/photos/6/90/69062/c04-142_16-qfn_sml.jpg)
PIC16F506T-I/MG
Manufacturer Part Number
PIC16F506T-I/MG
Description
1.5 KB Flash, 67 RAM, 12 I/O, Comparator, 8bit ADC 16 QFN 3x3x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC12F510-ISN.pdf
(124 pages)
Specifications of PIC16F506T-I/MG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
FLASH
Ram Size
67 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 54 of 124
- Download datasheet (3Mb)
PIC12F510/16F506
9.1.5
This ADC does not have a dedicated ADC clock, and
therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE and ADON bit will be cleared.
This will stop any conversion in process and power-
down the ADC module to conserve power. Due to the
nature of the conversion process, the ADRES may con-
tain a partial conversion. At least 1 bit must have been
converted prior to Sleep to have partial conversion data
in ADRES. The ADCS and CHS bits are reset to their
default condition; ANS<1:0> = 11 and CHS<1:0> = 11.
• For accurate conversions, T
• 500 ns < T
• T
Shaded areas indicate T
conversions. If analog input is desired at these
frequencies, use INTOSC/4 for the ADC clock source.
TABLE 9-2:
Note 1:
TABLE 9-3:
DS41268D-page 52
INTOSC
FOSC
FOSC
FOSC
Entering
Sleep
Wake or
Reset
Source
following:
AD
= 1/(F
When operating with external oscillator frequencies of 16 MHz or higher, better ADC performance will result
from selection of a suitable F
ADC clock.
SLEEP
OSC
AD
ADCS
<1:0>
Unchanged Unchanged
11
10
01
00
< 50 μs
/divisor)
ANS1
T
EFFECTS OF SLEEP ON ADCON0
1
AD
Divisor
FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
16
4
4
8
AD
out of range for accurate
ANS0
AD
1
.2 μs
.4 μs
.8 μs
20
MHz
must meet the
—
(1)
OSC
.25 μs
.5 μs
16
MHz
1 μs
ADCS1
—
(1)
divisor value from Table 9-2 than from use of the INTOSC/4 option for the
1
1
8 MHz 4 MHz 1 MHz
.5 μs
.5 μs
1 μs
2 μs
ADCS0
1
1
1 μs
1 μs
2 μs
4 μs
16 μs
4 μs
8 μs
—
CHS1
1
1
16 μs
32 μs
8 μs
kHz
500
—
CHS0
23 μs
46 μs
11 μs
kHz
350
1
1
—
© 2007 Microchip Technology Inc.
20 μs
40 μs
80 μs
GO/DONE
kHz
200
—
0
0
160 μs
40 μs
80 μs
kHz
100
—
ADON
32 kHz
125 μs
250 μs
500 μs
0
0
—
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