PIC16F506T-I/MG Microchip Technology, PIC16F506T-I/MG Datasheet - Page 76
![1.5 KB Flash, 67 RAM, 12 I/O, Comparator, 8bit ADC 16 QFN 3x3x0.9mm T/R](/photos/6/90/69062/c04-142_16-qfn_sml.jpg)
PIC16F506T-I/MG
Manufacturer Part Number
PIC16F506T-I/MG
Description
1.5 KB Flash, 67 RAM, 12 I/O, Comparator, 8bit ADC 16 QFN 3x3x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC12F510-ISN.pdf
(124 pages)
Specifications of PIC16F506T-I/MG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
FLASH
Ram Size
67 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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PIC12F510/16F506
BTFSS
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CALL
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
DS41268D-page 74
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0 ≤ b < 7
skip if (f<b>) = 1
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
[ label ] CALL k
0 ≤ k ≤ 255
(PC) + 1→ Top-of-Stack;
k → PC<7:0>;
(STATUS <6:5>) → PC<10:9>;
0 → PC<8>
Subroutine call. First, return
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS <6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
Clear f
[ label ] CLRF
0 ≤ f ≤ 31
00h → (f);
1 → Z
The contents of register ‘f’ are
cleared and the Z bit is set.
Subroutine Call
f
CLRW
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected: TO, PD
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
Clear W
[ label ] CLRW
None
00h → (W);
1 → Z
The W register is cleared. Zero bit
(Z) is set.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
Complement f
[ label ] COMF
0 ≤ f ≤ 31
d ∈ [0,1]
(f) → (dest)
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
© 2007 Microchip Technology Inc.
f,d
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