PIC16LF1823-I/ML Microchip Technology, PIC16LF1823-I/ML Datasheet - Page 279

• Manufacturer Part Number: PIC16LF1823-I/ML
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core, N
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1823-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.7
The MSSP1 module has a Baud Rate Generator avail-
able for clock generation in both I
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSP1ADD register
When a write occurs to SSP1BUF, the Baud Rate Gen-
erator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in
value from SSP1ADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 25-40:
TABLE 25-4:
 2010 Microchip Technology Inc.
Note 1:
Note: Values of 0x00, 0x01 and 0x02 are not valid
BAUD RATE GENERATOR
for SSP1ADD when used as a Baud Rate
Generator for I
limitation.
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
F
OSC
2
C interface does not conform to the 400 kHz I
MSSP1 CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C. This is an implementation
SSP1M<3:0>
Figure 25-39
SCL
2
C and SPI Master
PIC12F/LF1822/PIC16F/LF1823
(Register
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
SSP1M<3:0>
F
triggers the
CY
Control
Reload
25-6).
SSP1CLK
Preliminary
Reload
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP1 is
being operated in.
Table 25-4
instruction cycles and the BRG value loaded into
SSP1ADD.
EQUATION 25-1:
2
C specification (which applies to rates greater than
BRG Down Counter
SSP1ADD<7:0>
BRG Value
0Ch
4Fh
13h
19h
09h
27h
09h
F
CLOCK
demonstrates clock rates based on
=
-------------------------------------------------

SSPxADD
F
OSC
(2 Rollovers of BRG)
/2
F
OSC
400 kHz
400 kHz
DS41413B-page 279
308 kHz
100 kHz
308 kHz
100 kHz
100 kHz
F
+
CLOCK
1
 4  
(1)
(1)