PIC16LF1827-E/MV Microchip Technology, PIC16LF1827-E/MV Datasheet - Page 272
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PIC16LF1827-E/MV
Manufacturer Part Number
PIC16LF1827-E/MV
Description
7 KB Flash, 384 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1827-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF1826/27
24.6.8
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for T
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSPx module then goes into Idle mode
(Figure 24-29).
24.6.8.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 24-30:
DS41391C-page 272
BRG
) and the SCLx pin is deasserted (pulled high).
Note: T
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SSPxIF
BRG
SDAx
SCLx
Acknowledge sequence starts here,
= one Baud Rate Generator period.
ACKNOWLEDGE SEQUENCE WAVEFORM
SSPxIF set at
the end of receive
ACKEN = 1, ACKDT = 0
write to SSPxCON2
BRG
. The SCLx pin
8
D0
Preliminary
Cleared in
software
T
BRG
ACK
24.6.9
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit of the
SSPxSTAT register is set. A T
cleared and the SSPxIF bit is set (Figure 24-30).
24.6.9.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
BRG
9
SSPxIF set at the end
of Acknowledge sequence
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
(Baud Rate Generator rollover count)
2010 Microchip Technology Inc.
Cleared in
software
BRG
later, the PEN bit is
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