PIC16LF1847-E/ML Microchip Technology, PIC16LF1847-E/ML Datasheet - Page 282
![14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan](/photos/40/79/407995/pdip18_sml.jpg)
PIC16LF1847-E/ML
Manufacturer Part Number
PIC16LF1847-E/ML
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad
Core
PIC
Processor Series
PIC16LF
Data Bus Width
8 bit
Maximum Clock Frequency
32 MHz
Data Ram Size
256 B
Number Of Programmable I/os
15
Number Of Timers
ÿ4 x 8-bit, 1 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
Through Hole
Interface Type
SPI, I2C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC16(L)F1847
REGISTER 25-2:
DS41453B-page 282
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
R/C/HS-0/0
WCOL
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDAx and SCLx pins must be configured as inputs.
SSPxADD values of 0, 1 or 2 are not supported for I
SSPxADD value of 0 is not supported. Use SSPM = 0000 instead.
WCOL: Write Collision Detect bit
Master mode:
1 =
0 =
Slave mode:
1 =
0 =
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 =
0 =
In I
1 =
0 =
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 =
0 =
In I
1 =
0 =
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCLx release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0110 = I
0111 = I
1000 = I
1001 = Reserved
1010 = SPI Master mode, clock = F
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
R/C/HS-0/0
2
2
2
2
C mode:
C mode:
C Slave mode:
C Master mode:
SSPOV
A write to the SSPxBUF register was attempted while the I
No collision
The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
No collision
A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
No overflow
A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
No overflow
Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
SSPxCON1: SSPx CONTROL REGISTER 1
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C firmware controlled Master mode (Slave idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
SSPEN
OSC
OSC
OSC
OSC
OSC
(1)
/4
/16
/64
/(4 * (SSPxADD+1))
/ (4 * (SSPxADD+1))
R/W-0/0
CKP
Preliminary
2
C™ mode.
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
R/W-0/0
(5)
(4)
2
C™ conditions were not valid for a transmission to be started
R/W-0/0
SSPM<3:0>
2011 Microchip Technology Inc.
C = User cleared
R/W-0/0
(3)
(2)
R/W-0/0
bit 0
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