PIC16LF1902-E/SP Microchip Technology, PIC16LF1902-E/SP Datasheet - Page 188
![3.5KB Flash, 128B RAM, LCD, 11x10b ADC, NanoWatt XLP 28 SPDIP .300in TUBE](/photos/16/11/161110/pdip28_sml.jpg)
PIC16LF1902-E/SP
Manufacturer Part Number
PIC16LF1902-E/SP
Description
3.5KB Flash, 128B RAM, LCD, 11x10b ADC, NanoWatt XLP 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1902-EMV.pdf
(240 pages)
Specifications of PIC16LF1902-E/SP
Processor Series
PIC16LF190x
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
2 KB
Data Ram Size
128 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-28
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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PIC16LF1902/3
BCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
BRA
Syntax:
Operands:
Operation:
Status Affected:
Description:
BRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
BSF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41455B-page 188
Relative Branch
[ label ] BRA label
[ label ] BRA $+k
-256 label - PC + 1 255
-256 k 255
(PC) + 1 + k PC
None
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion. This branch has a limited range.
Bit Clear f
[ label ] BCF
0 f 127
0 b 7
0 (f<b>)
None
Bit ‘b’ in register ‘f’ is cleared.
Relative Branch with W
[ label ] BRW
None
(PC) + (W) PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
Bit Set f
[ label ] BSF
0 f 127
0 b 7
1 (f<b>)
None
Bit ‘b’ in register ‘f’ is set.
f,b
f,b
Preliminary
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Clear
[ label ] BTFSC f,b
0 f 127
0 b 7
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘ 1 ’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘ 0 ’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 f 127
0 b < 7
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘ 0 ’, the next
instruction is executed.
If bit ‘b’ is ‘ 1 ’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
2011 Microchip Technology Inc.
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