PIC16LF1903T-I/SO Microchip Technology, PIC16LF1903T-I/SO Datasheet - Page 65

• Manufacturer Part Number: PIC16LF1903T-I/SO
• Description: 7KB Flash, 256B RAM, LCD, 11x10b ADC, NanoWatt XLP 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1903T-I/SO

• Processor Series: PIC16LF190x
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: -
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: -
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

7.3
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the
“Power-Down Mode (Sleep)”
7.4
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s appli-
cation, other registers may also need to be saved.
 2011 Microchip Technology Inc.
Interrupts During Sleep
INT Pin
Automatic Context Saving
for more details.
Section 8.0
Preliminary
PIC16LF1902/3
DS41455B-page 65