PIC16LF1906T-I/SS Microchip Technology, PIC16LF1906T-I/SS Datasheet - Page 163

• Manufacturer Part Number: PIC16LF1906T-I/SS
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906T-I/SS

• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16-bit, 1 x 8-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

FIGURE 18-5:
TABLE 18-2:
 2011 Microchip Technology Inc.
BAUD1CON
BAUD2CON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TRISC
TXSTA
Legend:
Note 1:
Name
Note:
RX/DT pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
RCIDL
*
Page provides register information.
PIC16LF1904/7 only.
— = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
This timing diagram shows three words appearing on the RX/DT input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TMR1GIE
TMR1GIF
ABDOVF
ABDOVF
TRISC7
CSRC
SPEN
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
GIE
Start
ASYNCHRONOUS RECEPTION
bit
bit 0
TRISC6
RCIDL
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
bit 1
EUSART Baud Rate Generator, High Byte
TMR0IE
EUSART Baud Rate Generator, Low Byte
TRISC5
RCIE
RCIF
SREN
TXEN
Bit 5
—
—
bit 7/8
(1)
(1)
EUSART Receive Register
Preliminary
Stop
TRISC4
bit
TXIE
TXIF
CREN
SCKP
SCKP
SYNC
INTE
Bit 4
Word 1
RCREG
(1)
(1)
Start
bit
ADDEN
TRISC3
SENDB
bit 0
BRG16
BRG16
IOCIE
Bit 3
—
—
TMR0IF
TRISC2
PIC16LF1904/6/7
BRGH
bit 7/8 Stop
FERR
Word 2
RCREG
Bit 2
—
—
—
—
bit
TRISC1
Start
OERR
TRMT
WUE
WUE
Bit 1
INTF
bit
—
—
TMR1IE
TMR1IF
TRISC0
ABDEN
ABDEN
IOCIF
RX9D
TX9D
bit 7/8
Bit 0
DS41569A-page 163
Stop
bit
Register
on Page
160*
167*
167*
166
166
165
134
164
93
94
98