PIC16LF737-I/ML Microchip Technology, PIC16LF737-I/ML Datasheet - Page 123
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF737-I/ML
Manufacturer Part Number
PIC16LF737-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF737-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.4.8
To initiate a Start condition, the user sets the Start
Condition Enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the Baud Rate
Generator
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (T
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit (SSPSTAT<3>) to
be set. Following this, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
resumes its count. When the Baud Rate Generator
times out (T
automatically cleared by hardware, the Baud Rate
Generator is suspended, leaving the SDA line held low
and the Start condition is complete.
FIGURE 10-19:
2004 Microchip Technology Inc.
Note:
I
CONDITION TIMING
BRG
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I
BRG
2
2
is
C module is reset into its Idle state.
C MASTER MODE START
), the SDA pin is driven low. The action
), the SEN bit (SSPCON2<0>) will be
reloaded
Write to SEN bit occurs here
FIRST START BIT TIMING
with
SDA
SCL
the
contents
SDA = 1,
SCL = 1
T
BRG
of
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
10.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
and sets SSPIF bit
Note:
T
Write to SSPBUF occurs here
BRG
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
1st bit
WCOL Status Flag
T
BRG
PIC16F7X7
2nd bit
DS30498C-page 121
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