PIC16LF737-I/ML Microchip Technology, PIC16LF737-I/ML Datasheet - Page 29
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF737-I/ML
Manufacturer Part Number
PIC16LF737-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF737-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.2.2.7
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-7:
2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR2 Register
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)
OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software)
0 = System clock operating
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software)
0 = The supply voltage is greater then the specified LVD voltage
Unimplemented: Read as ‘0’
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP when configured for I
0 = No bus collision has occurred
Unimplemented: Read as ‘0’
CCP3IF: CCP3 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused.
Legend:
R = Readable bit
-n = Value at POR
bit 7
OSFIF
R/W-0
R/W-0
CMIF
R/W-0
LVDIF
W = Writable bit
‘1’ = Bit is set
U-0
—
Note:
R/W-0
BCLIF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
U-0
—
2
C Master mode
PIC16F7X7
CCP3IF
x = Bit is unknown
R/W-0
DS30498C-page 27
CCP2IF
R/W-0
bit 0
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