PIC18F1230-E/SS Microchip Technology, PIC18F1230-E/SS Datasheet - Page 175

• Manufacturer Part Number: PIC18F1230-E/SS
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1230-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

 2009 Microchip Technology Inc.
16.3
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
Acquisition time may be set with the ACQT2:ACQT0 bits
(ADCON2<5:3>), which provide a range of 2 to 20 T
When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
Manual
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 16-1:
Note 1:
2:
3:
4:
Selecting and Configuring
Acquisition Time
Operation
The RC source has a typical T
The RC source has a typical T
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
Low-power (PIC18LF1230/1330) devices only.
16 T
32 T
64 T
acquisition
2 T
4 T
8 T
RC
OSC
OSC
OSC
OSC
OSC
OSC
(3)
AD Clock Source (T
T
AD
vs. DEVICE OPERATING FREQUENCIES
is
selected
ADCS2:ADCS0
AD
)
AD
AD
000
100
001
101
010
110
x11
time of 1.2
time of 2.5
when
AD
.


s.
s.
16.4
The A/D conversion time per bit is defined as T
A/D conversion requires 11 T
The source of the A/D conversion clock is software
selectable. There are seven possible options for T
• 2 T
• 4 T
• 8 T
• 16 T
• 32 T
• 64 T
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
minimum
information).
Table 16-1 shows the resultant T
the device operating frequencies and the A/D clock
source selected.
PIC18F1230/1330
AD
11.43 MHz
22.86 MHz
) must be as short as possible, but greater than the
1.00 MHz
2.86 MHz
5.71 MHz
40.0 MHz
40.0 MHz
OSC
OSC
OSC
OSC
OSC
OSC
Selecting the A/D Conversion
Clock
PIC18F1230/1330
Maximum Device Frequency
T
AD
(1)
(see
parameter
PIC18LF1230/1330
AD
per 10-bit conversion.
AD
1.00 MHz
11.43 MHz
22.86 MHz
22.86 MHz
1.43 MHz
2.86 MHz
5.72 MHz
DS39758D-page 175
times derived from
130
(2)
for
AD
(4)
. The
more
AD
: