PIC18F2221-E/SP Microchip Technology, PIC18F2221-E/SP Datasheet - Page 140

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PIC18F2221-E/SP

Manufacturer Part Number
PIC18F2221-E/SP
Description
4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2221-E/SP

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2221/2321/4221/4321 FAMILY
14.2
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match)
provides the input for the 4-bit output counter/post-
scaler. This counter generates the TMR2 match inter-
rupt flag which is latched in TMR2IF (PIR1<1>). The
interrupt is enabled by setting the TMR2 Match Inter-
rupt Enable bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 14-1:
TABLE 14-1:
DS39689F-page 140
INTCON GIE/GIEH PEIE/GIEL
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1:
Name
T2OUTPS<3:0>
T2CKPS<1:0>
F
OSC
Timer2 Interrupt
/4
Timer2 Register
Timer2 Period Register
These bits are unimplemented on 28-pin devices and read as ‘0’.
PSPIE
PSPIP
PSPIF
Bit 7
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
(1)
(1)
(1)
TIMER2 BLOCK DIAGRAM
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Internal Data Bus
1:1, 1:4, 1:16
ADIE
ADIP
ADIF
Bit 6
2
Prescaler
TMR0IE
RCIF
RCIE
RCIP
Bit 5
4
TMR2
INT0IE
TXIE
TXIP
Bit 4
TXIF
Reset
8
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
14.3
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 18.0
“Master Synchronous Serial Port (MSSP) Module”.
Comparator
1:1 to 1:16
Postscaler
8
TMR2/PR2
Match
Timer2 Output
TMR0IF
CCP1IF
CCP1IE
CCP1IP
Bit 2
TMR2IF
TMR2IE
TMR2IP
INT0IF
© 2009 Microchip Technology Inc.
Bit 1
PR2
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
TMR1IF
TMR1IE
TMR1IP
RBIF
Bit 0
on page
Values
Reset
55
58
58
58
56
56
56

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