PIC18F23K22-I/SO Microchip Technology, PIC18F23K22-I/SO Datasheet - Page 169

• Manufacturer Part Number: PIC18F23K22-I/SO
• Description: 8KB, Flash, 768bytes-RAM,8-bit Family 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F23K22-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Processor Series: PIC18F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 12-7:
12.12 Peripheral Module Disable
When a peripheral module is not used or inactive, the
module can be disabled by setting the Module Disable
bit in the PMD registers. This will reduce power con-
sumption to an absolute minimum. Setting the PMD
bits holds the module in Reset and disconnects the
module’s clock source. The Module Disable bits for
Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5
(TMR5MD) are in the PMD0 Register. See
“Power-Managed Modes”
 2010 Microchip Technology Inc.
TIMER1/3/5
TMRxGIF
TMRxGE
TxGSPM
TxGPOL
TxGVAL
TxGGO/
TxG_IN
TxGTM
DONE
TxCKI
TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
Cleared by software
N
for more information.
Counting enabled on
rising edge of TxG
Set by software
Section 3.0
Preliminary
N + 1
falling edge of TxGVAL
Set by hardware on
N + 2
PIC18(L)F2X/4XK22
N + 3
N + 4
Cleared by hardware on
falling edge of TxGVAL
DS41412D-page 169
Cleared by
software