PIC18F44K20-E/MV Microchip Technology, PIC18F44K20-E/MV Datasheet - Page 308
![16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU](/photos/16/15/161538/qfn-40_sml.jpg)
PIC18F44K20-E/MV
Manufacturer Part Number
PIC18F44K20-E/MV
Description
16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K20T-ISS.pdf
(456 pages)
Specifications of PIC18F44K20-E/MV
Processor Series
PIC18
Core
PIC18F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
512 B
Interface Type
I2C, SPI, SCI, USB, MSSP, RJ11
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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PIC18F2XK20/4XK20
23.2
For PIC18F2XK20/4XK20 devices, the WDT is driven
by the LFINTOSC source. When the WDT is enabled,
the clock source is also enabled. The nominal WDT
period is 4 ms and has the same stability as the LFIN-
TOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has occurred.
FIGURE 23-1:
DS41303G-page 308
Change on IRCF bits
Note 1: The CLRWDT and SLEEP instructions
All Device Resets
LFINTOSC Source
2: Changing the setting of the IRCF bits of
3: When a CLRWDT instruction is executed,
WDTPS<3:0>
Watchdog Timer (WDT)
clear the WDT and postscaler counts
when executed.
the OSCCON register clears the WDT
and postscaler counts.
the postscaler count will be cleared.
SWDTEN
CLRWDT
WDTEN
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
128
4
Programmable Postscaler
1:1 to 1:32,768
Reset
2010 Microchip Technology Inc.
WDT
Reset
Wake-up
from Power
Managed Modes
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