PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 159

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 11-2:
11.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
TABLE 11-1:
 2010 Microchip Technology Inc.
INTCON
INTCON2
T0CON
TMR0H
TMR0L
TRISA
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer0.
Note:
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
Name
Prescaler
register
T0SE
T0CS
T0PS<2:0>
PSA
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
GIE/GIEH PEIE/GIEL TMR0IE
F
TMR0ON
TRISA7
OSC
RBPU
Bit 7
REGISTERS ASSOCIATED WITH TIMER0
/4
which
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
1
INTEDG0 INTEDG1 INTEDG2
TRISA6
determine
T08BIT
Bit 6
Programmable
Prescaler
TRISA5
3
the
T0CS
Bit 5
prescaler
Timer0 Register, High Byte
Timer0 Register, Low Byte
1
0
Preliminary
TRISA4
INT0IE
T0SE
Bit 4
(2 T
Sync with
Internal
Clocks
CY
Delay)
TRISA3
11.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clear-
ing the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
RBIE
Bit 3
PSA
—
PIC18(L)F2X/4XK22
Timer0 Interrupt
TMR0IF
TMR0IP
TRISA2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
TMR0L
8
8
T0PS<2:0>
TRISA1
INT0IF
Bit 1
High Byte
TMR0H
—
TMR0
8
8
8
TRISA0
RBIP
RBIF
Bit 0
DS41412D-page 159
Set
TMR0IF
on Overflow
Read TMR0L
Write TMR0L
Internal Data Bus
on page
Values
Reset
157
154
115
116
—
—