PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 29

16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R

PIC18F64J11T-I/PT

Manufacturer Part Number
PIC18F64J11T-I/PT
Description
16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F64J11T-I/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F64J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 5-5:
 2009 Microchip Technology Inc.
CFGB80 = Byte sum of [(CW1 & 04E1h) + (CW2 & 0FC7h) + (CW3 & 03F8h)]
CFGB60 = Byte sum of [(CW1 & 04E1h) + (CW2 & 0FC7h) + (CW3 & 0100h)]
Legend: Item
CFGB = Byte sum of [(CW1 & 0CE1h) + (CW2 & 0FC7h) + (CW3 & 0100h)]
Note:
PIC18F85J90
PIC18F87J10
Family
SUM(a:b) =
+
CW
CFGB
CW3 address is the last location – 2 of implemented program memory; CW2 is the last location – 4;
CW1 is the last location – 6.
CHECKSUM EQUATION FOR PIC18F6XJXX/8XJXX (CONTINUED)
=
=
=
PIC18F63J90
PIC18F64J90
PIC18F64J95
PIC18F65J90
PIC18F83J90
PIC18F84J90
PIC18F84J95
PIC18F85J90
PIC18F65J10
PIC18F65J15
PIC18F66J10
PIC18F66J15
PIC18F67J10
PIC18F85J10
PIC18F85J15
PIC18F86J10
PIC18F86J15
PIC18F87J10
Description
Byte sum of locations a to b inclusive (all 3 bytes of code memory)
Addition
Configuration Word
Configuration Block (Masked)
Device
Read Code Protection
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
PIC18F6XJXX/8XJXX
CFGB60 + SUM(00000:17FF7h)
CFGB60 + SUM(00000:1FFF7h)
CFGB80 + SUM(00000:17FF7h)
CFGB80 + SUM(00000:1FFF7h)
CFGB60 + SUM(0000:BFF7h)
CFGB60 + SUM(0000:FFF7h)
CFGB80 + SUM(0000:BFF7h)
CFGB80 + SUM(0000:FFF7h)
CFGB60 + SUM(0000:7FF7h)
CFGB80 + SUM(0000:7FF7h)
CFGB + SUM(0000:1FF7h)
CFGB + SUM(0000:3FF7h)
CFGB + SUM(0000:5FF7h)
CFGB + SUM(0000:7FF7h)
CFGB + SUM(0000:1FF7h)
CFGB + SUM(0000:3FF7h)
CFGB + SUM(0000:5FF7h)
CFGB + SUM(0000:7FF7h)
Checksum Computation
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
DS39644L-page 29

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