PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 450

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
FIGURE 28-16:
TABLE 28-21: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
DS39775C-page 450
Param
70
70A
71
71A
72
72A
73
73A
74
75
76
77
78
79
80
81
82
83
Note 1:
No.
Note:
(CKP = 0)
(CKP = 1)
SDI
SDIx
SCKx
SDOx
SSx
SCKx
2:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SS
SS
SS
SC
SC
SC
SC
SS
SC
SC
SC
SC
SS
SC
SC
DI
DI
B
DO
DO
DO
DO
Symbol
2
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
V2
V2
L2
Refer to Figure 28-3 for load conditions.
L2
L2
L2WB
H2
H2
L2
H2
L2
H
L
H2
L2
R
F
B
V2
V2
R
F
DO
SC
SC
SC
SC
DO
SS
DI
DO
SS
DO
DI
SC
SC
L
H
H,
L
L,
V
H,
L
V
H,
V,
H,
L
Z SSx ↑ to SDOx Output High-Impedance
SSx ↓ to SCKx ↓ or SCKx ↑ Input
SSx ↓ to Write to SSPxBUF
SCKx Input High Time
(Slave mode)
SCKx Input Low Time
(Slave mode)
Setup Time of SDIx Data Input to SCKx Edge
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDIx Data Input to SCKx Edge
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
SDOx Data Output Valid after SCKx Edge
SDOx Data Output Setup to SCKx Edge
SDOx Data Output Valid after SSx ↓ Edge
SSx ↑ after SCKx Edge
82
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
70
73
MSb In
MSb
74
71
75, 76
Characteristic
72
bit 6 - - - - - - 1
bit 6 - - - - 1
Continuous
Single byte
Continuous
Single byte
80
LSb
LSb In
1.25 T
1.25 T
1.5 T
3 T
3 T
Min
100
100
T
CY
CY
40
40
10
—
—
—
—
—
—
CY
CY
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
© 2009 Microchip Technology Inc.
77
Max Units Conditions
25
50
25
25
50
50
—
—
—
—
—
—
—
—
—
25
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)