PIC18F86J55T-I/PT Microchip Technology, PIC18F86J55T-I/PT Datasheet - Page 278

• Manufacturer Part Number: PIC18F86J55T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J55T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J55T-I/PTTR

PIC18F87J50 FAMILY
TABLE 19-4:
DS39775C-page 278
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISD
SSP1BUF
SSP1ADD
SSPxMSK
SSPxCON1
SSPxCON2
SSPxSTAT
SSP2BUF
SSP2ADD
Legend:
Note 1:
Name
2:
(1)
— = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
operating modes in 7-bit Masking mode. See Section 19.4.3.4 “7-Bit Address Masking Mode” for more details.
Alternate bit definitions for use in I
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
GIE/GIEH PEIE/GIEL
OSCFIF
OSCFIE
OSCFIP
TRISC7
TRISD7
SSP2IF
SSP2IE
SSP2IP
PMPIE
PMPIP
PMPIF
WCOL
GCEN
GCEN
MSK7
Bit 7
SMP
REGISTERS ASSOCIATED WITH I
ACKSTAT
ACKSTAT ADMSK5
TRISC6
TRISD6
BCL2IF
BCL2IE
BCL2IP
SSPOV
CM2IF
CM2IE
CM2IP
MSK6
ADIF
ADIE
ADIP
Bit 6
CKE
2
TMR0IE
TRISC5
TRISD5
SSPEN
ACKDT
CM1IE
CM1IP
2
RC1IF
RC1IE
RC1IP
CM1IF
RC2IF
RC2IE
RC2IP
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
MSK5
C Slave mode), MSSP2 Baud Rate Reload Register (I
Bit 5
D/A
2
C Slave mode operations only.
(2)
ADMSK4
TRISC4
TRISD4
ACKEN
INT0IE
USBIE
USBIP
USBIF
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
MSK4
Bit 4
CKP
P
2
(2)
C™ OPERATION
ADMSK3
TMR4IE
TMR4IP
SSP1IE
SSP1IP
TMR4IF
TRISC3
TRISD3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
SSPM3
RCEN
MSK3
RBIE
Bit 3
S
(2)
ADMSK2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
TRISC2
TRISD2
SSPM2
LVDIF
LVDIE
LVDIP
MSK2
Bit 2
PEN
R/W
(2)
ADMSK1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
CCP4IE
CCP4IP
CCP4IF
TRISC1
TRISD1
SSPM1
INT0IF
© 2009 Microchip Technology Inc.
RSEN
MSK1
Bit 1
UA
2
2
2
C Master mode)
C Master mode)
C™ mode.
(2)
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISD0
SSPM0
MSK0
RBIF
Bit 0
SEN
SEN
BF
2
C™ Slave
on Page:
Values
Reset
62, 65
62, 65
62, 65
64
64
64
65
65
61
64
64
64
64
64
64
64
64
62
62
65