PIC18F87J90T-I/PT Microchip Technology, PIC18F87J90T-I/PT Datasheet - Page 80

• Manufacturer Part Number: PIC18F87J90T-I/PT
• Description: Segmented LCD, 128KB Flash, 4KB RAM, 12 MIPS, NanoWatt 80 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J90T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J90 FAMILY
TABLE 6-3:
DS39933D-page 80
RTCVALL
ALRMCFG
ALRMRPT
ALRMVALH
ALRMVALL
CTMUCONH
CTMUCONL
CTMUICON
PADCFG1
Legend:
Note 1:
File Name
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
RTCC Value Low Register Window based on RTCPTR<1:0>
Alarm Value High Register Window based on ALRMPTR<1:0>
Alarm Value Low Register Window based on ALRMPTR<1:0>
EDG2POL
CTMUEN
ALRMEN
ARPT7
ITRIM5
Bit 7
—
PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
EDG2SEL1 EDG2SEL0
CHIME
ARPT6
ITRIM4
Bit 6
—
—
CTMUSIDL
AMASK3
ITRIM3
ARPT5
Bit 5
—
EDG1POL
AMASK2
ARPT4
ITRIM2
TGEN
Bit 4
—
EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 0000
AMASK1
EDGEN
ARPT3
ITRIM1
Bit 3
—
RTSECSEL1 RTSECSEL0
EDGSEQEN
AMASK0
ARPT2
ITRIM0
Bit 2
2
C™ Slave mode. See Section 18.4.3.2 “Address
ALRMPTR1 ALRMPTR0 0000 0000
IDISSEN
ARPT1
IRNG1
Bit 1
 2010 Microchip Technology Inc.
CTTRIG
ARPT0
IRNG0
Bit 0
—
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
---- -00-
POR, BOR
Value on
Details on
64, 160
64, 159
64, 160
64, 163
64, 163
64, 321
64, 322
64, 323
64, 158
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