PIC18F96J60-I/PT Microchip Technology, PIC18F96J60-I/PT Datasheet - Page 451

• Manufacturer Part Number: PIC18F96J60-I/PT
• Description: 64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J60-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 12 KB
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 27-27: A/D CONVERSION REQUIREMENTS
27.5
TABLE 27-28: REQUIREMENTS FOR ETHERNET TRANSCEIVER EXTERNAL MAGNETICS
© 2009 Microchip Technology Inc.
130
131
132
135
TBD
Legend: TBD = To Be Determined
Note 1:
Param
RX Turns Ratio
TX Turns Ratio
Insertion Loss
Primary Inductance
Transformer Isolation
Differential to Common-Mode
Rejection
Return Loss
No.
2:
3:
4:
T
T
T
T
T
Symbol
Ethernet Specifications and Requirements
AD
CNV
ACQ
SWC
DIS
Parameter
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Discharge Time
Characteristic
DD
Min
350
1.5
-16
40
to V
—
—
—
SS
or V
Norm
1:1
1:1
—
—
—
—
—
SS
to V
DD
Max
-1.1
). The source impedance (R
—
—
—
—
—
—
CY
PIC18F97J60 FAMILY
cycle.
TBD
Min
0.7
1.4
0.2
11
—
kVrms Required to meet IEEE 802.3 requirements
Units
dB
μH
dB
dB
—
—
(Note 4)
25.0
Max
Transformer Center Tap = 3.3V
8 mA bias
0.1 to 10 MHz
12
—
—
1
(1)
Units
T
μs
μs
μs
μs
AD
S
) on the input channels is 50Ω.
T
A/D RC mode
-40°C to +85°C
Conditions
OSC
AD
based, V
clock divider.
Conditions
DS39762E-page 451
REF
≥ 2.0V