PIC18LF14K22-E/P Microchip Technology, PIC18LF14K22-E/P Datasheet - Page 79
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PIC18LF14K22-E/P
Manufacturer Part Number
PIC18LF14K22-E/P
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.0
There are up to three ports available. Some pins of the
I/O ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
• LAT register (output latch)
The PORTA Data Latch (LATA register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 8-1.
FIGURE 8-1:
2010 Microchip Technology Inc.
device)
Note 1:
RD LAT
Data
Bus
WR LAT
or Port
WR TRIS
RD TRIS
RD Port
I/O PORTS
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
GENERIC I/O PORT
OPERATION
Q
Q
Q
EN
EN
D
DD
and V
I/O pin
Buffer
Input
SS
.
(1)
Preliminary
PIC18F1XK22/LF1XK22
8.1
PORTA is 5 bits wide. PORTA<5:4,2:0> bits are
bidirectional ports and PORTA is an input-only port.
The corresponding data direction register is TRISA.
Setting a TRISA bit (= 1) will make the corresponding
PORTA pin an input (i.e., disable the output driver).
Clearing a TRISA bit (= 0) will make the corresponding
PORTA pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the PORT latch.
The PORTA Data Latch (LATA) register is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
All of the PORTA pins are individually configurable as
interrupt-on-change pins. Control bits in the IOCA
register enable (when set) or disable (when clear) the
interrupt function for each pin.
When set, the RABIE bit of the INTCON register
enables interrupts on all pins which also have their
corresponding IOCA bit set. When clear, the RABIE
bit disables all interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any pin configured as an output is
excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt flag
bit (RABIF) in the INTCON register.
PORTA, TRISA and LATA
Registers
DS41365D-page 79
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