PIC24FJ64GA102-E/SS Microchip Technology, PIC24FJ64GA102-E/SS Datasheet - Page 160

• Manufacturer Part Number: PIC24FJ64GA102-E/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GA102-E/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 300 mA
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC24FJ64GA104 FAMILY
14.4
The DCB bits (OCxCON2<10:9>) provide for resolution
better than one instruction cycle. When used, they
delay the falling edge generated by a match event by a
portion of an instruction cycle.
For example, setting DCB<1:0> = 10 causes the falling
edge to occur half way through the instruction cycle in
which the match event occurs, instead of at the
beginning.
OCM<2:0> = 001. When operating the module in PWM
mode (OCM<2:0> = 110 or 111), the DCB bits will be
double-buffered.
TABLE 14-1:
TABLE 14-2:
DS39951C-page 160
Prescaler Ratio
Period Value
Resolution (bits)
Note 1:
Prescaler Ratio
Period Value
Resolution (bits)
Note 1:
PWM Frequency
PWM Frequency
Subcycle Resolution
Based on F
Based on F
These
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (F
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F
bits
CY
CY
= F
= F
cannot
OSC
OSC
30.5 Hz
FFFFh
/2; Doze mode and PLL are disabled.
FFFFh
/2; Doze mode and PLL are disabled.
7.6 Hz
16
16
8
8
be
used
244 Hz
FFFFh
FFFFh
61 Hz
16
16
1
1
when
122 Hz
488 Hz
7FFFh
7FFFh
15
15
1
1
The DCB bits are intended for use with a clock source
identical to the system clock. When an OCx module
with enabled prescaler is used, the falling edge delay
caused by the DCB bits will be referenced to the
system clock period, rather than the OCx module's
period.
3.9 kHz
977 Hz
0FFFh
0FFFh
12
12
1
1
15.6 kHz
3.9 kHz
03FFh
03FFh
10
10
1
1
 2010 Microchip Technology Inc.
31.3 kHz
125 kHz
007Fh
007Fh
CY
1
7
CY
1
7
= 4 MHz)
= 16 MHz)
125 kHz
500 kHz
001Fh
001Fh
(1)
1
5
1
5
(1)