PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 229
PIC24FJ64GB002-I/SS
Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Specifications of PIC24FJ64GB002-I/SS
Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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18.7.3
REGISTER 18-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15)
2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
LSPD
R/W-0
U-0
—
(1)
These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits
are always unimplemented and read as ‘0’.
USB ENDPOINT MANAGEMENT REGISTERS
RETRYDIS
Unimplemented: Read as ‘0’
LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)
1 = Direct connection to a low-speed device is enabled
0 = Direct connection to a low-speed device is disabled
RETRYDIS: Retry Disable bit (U1EP0 only)
1 = Retry NAK transactions are disabled
0 = Retry NAK transactions are enabled; retry done in hardware
Unimplemented: Read as ‘0’
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN and EPRXEN = 1:
1 = Disable Endpoint n from Control transfers; only Tx and Rx transfers are allowed
0 = Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also are allowed.
For all other combinations of EPTXEN and EPRXEN:
This bit is ignored.
EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive is enabled
0 = Endpoint n receive is disabled
EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit is enabled
0 = Endpoint n transmit is disabled
EPSTALL: Endpoint Stall Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake is enabled
0 = Endpoint handshake is disabled (typically used for isochronous endpoints)
R/W-0
U-0
—
(1)
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
EPCONDIS
R/W-0
U-0
PIC24FJ64GB004 FAMILY
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EPRXEN
R/W-0
U-0
—
EPTXEN
(1)
R/W-0
U-0
—
x = Bit is unknown
EPSTALL
R/W-0
U-0
—
DS39940D-page 229
EPHSHK
R/W-0
U-0
—
bit 8
bit 0
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