SST25VF080B-80-4I-SAE Microchip Technology, SST25VF080B-80-4I-SAE Datasheet
SST25VF080B-80-4I-SAE
Specifications of SST25VF080B-80-4I-SAE
Related parts for SST25VF080B-80-4I-SAE
SST25VF080B-80-4I-SAE Summary of contents
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... SST's 25 series Serial Flash family features a four-wire, SPI-compatible inter- face that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF080B devices are enhanced with improved operating frequency which lowers power consump- tion. SST25VF080B SPI serial flash memories are manufactured with SST's proprietary, high-performance CMOS SuperFlash technology ...
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... The SST25VF080B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for SST25VF080B. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro- gram and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies ...
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... Block Diagram Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc Decoder Address Buffers and Latches Control Logic Serial Interface CE# SCK Mbit SPI Serial Flash SST25VF080B Data Sheet SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1296 B1.0 WP# HOLD# S71296-05-000 02/11 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To temporarily stop serial communication with SPI flash memory without reset- ting the device. To provide power supply voltage: 2.7-3.6V for SST25VF080B 4 8 Mbit SPI Serial Flash SST25VF080B ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF080B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... Figure 4: Hold Condition Waveform Write Protection SST25VF080B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for the Block-Protection description ...
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... Indicate current level of block write protection (See Table 4) Indicate current level of block write protection (See Table 4) Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP3, BP2, BP1, BP0 are read-only bits 0 = BP3, BP2, BP1, BP0 are read/writable 7 SST25VF080B Data Sheet Default at Power-up Read/Write ...
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... BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (V ), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset Table 4: Software Status Register Block Protection for SST25VF080B Protection Level None Upper 1/16 Upper 1/8 ...
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... A Microchip Technology Company Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF080B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut- ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write- Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. Read (25/33 MHz) The Read instruction, 03H, supports MHz (for SST25VF080B-50-xx-xxxx MHz (for SST25VF080B-80-xx-xxxx) Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE# ...
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... A Microchip Technology Company High-Speed-Read (66/80 MHz) The High-Speed-Read instruction supporting MHz (for SST25VF080B-50-xx-xxxx MHz (for SST25VF040B-80-xx-xxxx) Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High- Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence. ...
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... Byte-Program operation. See Figure 7 for the Byte-Program sequence. Figure 7: Byte-Program Sequence ©2011 Silicon Storage Technology, Inc. CE# MODE SCK MODE 0 02 ADD. SI MSB MSB SO HIGH IMPEDANCE 12 8 Mbit SPI Serial Flash SST25VF080B Data Sheet -A ]. Following the address, the data for the completion ADD. ADD MSB LSB 1296 ByteProg ...
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... Enable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/ BY# status during the AAI command. See Figures 9 and 10. ©2011 Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash -A ] with The Hardware End-of-Write detection method is described in the BP. 13 SST25VF080B Data Sheet BP Fol with A =0, the second 23 ...
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... Figure 8: Enable SO as Hardware RY/BY# During AAI Programming Figure 9: Disable SO as Hardware RY/BY# During AAI Programming ©2011 Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1271 EnableSO.0 CE# MODE MODE 0 SCK 80 SI MSB HIGH IMPEDANCE SO 1271 DisableSO.0 14 SST25VF080B Data Sheet S71296-05-000 02/11 ...
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... Check for Flash Busy Status to load next valid 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming register to load next valid Mbit SPI Serial Flash SST25VF080B Check for Flash Busy Status to load next valid command ...
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... Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash -A ]. Address bits [ remaining address bits can CE# MODE SCK MODE ADD. MSB MSB SO HIGH IMPEDANCE 16 SST25VF080B Data Sheet = Most Significant address) are used CE# must be driven high IL IH ADD. ADD. 1296 SecErase.0 S71296-05-000 02/11 ...
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... CE# must be driven high before the instruction is executed. The 64-KByte Block- IL IH. ), remaining address bits can CE# MODE SCK MODE MSB SO HIGH IMPEDANCE CE# MODE SCK MODE MSB SO HIGH IMPEDANCE 17 8 Mbit SPI Serial Flash SST25VF080B - Address bits CE# must ADDR ADDR ADDR MSB 1296 32KBklEr ADDR ADDR ADDR MSB 1296 63KBlkEr ...
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... Figure 16:Read-Status-Register (RDSR) Sequence ©2011 Silicon Storage Technology, Inc. CE# MODE SCK MODE MSB SO HIGH IMPEDANCE MSB HIGH IMPEDANCE 18 8 Mbit SPI Serial Flash SST25VF080B 1296 ChEr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1296 RDSRseq.0 S71296-05-000 Data Sheet 02/11 ...
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... CE# must be driven high before the WRDI instruction is executed. Figure 18:Write Disable (WRDI) Sequence ©2011 Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash CE# MODE SCK MODE MSB SO HIGH IMPEDANCE 1296 WREN.0 CE# MODE SCK MODE MSB SO HIGH IMPEDANCE 1296 WRDI.0 19 SST25VF080B Data Sheet after executing the WRDI BP S71296-05-000 02/11 ...
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... Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence ©2011 Silicon Storage Technology, Inc. ) prior to the low-to-high transition of the CE# pin at the end MODE 3 MODE MSB MSB HIGH IMPEDANCE 20 8 Mbit SPI Serial Flash SST25VF080B Data Sheet STATUS REGISTER MSB 1296 EWSR.0 S71296-05-000 02/11 ...
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... Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 8EH, identifies the device as SST25VF080B. The instruction sequence is shown in Figure 20. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output ...
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... A Microchip Technology Company Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF080B and manufacturer as SST. This command is backward compatible and should be used as default device identification when multi- ple versions of SPI Serial Flash devices are used in a design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A instruction, the manufacturer’ ...
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... Output Short Circuit Current 1. Output shorted for no more than one second. No more than one output shorted at a time. Table 8: Operating Range Range Commercial Industrial Table 9: AC Conditions of Test 1. See Figures 26 and 27 Table 10:DC Operating Characteristics (SST25VF080B-50-xx-xxxx) Symbol Parameter I Read Current DDR I Read Current DDR2 ...
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... A Microchip Technology Company Table 11:DC Operating Characteristics (SST25VF080B-80-xx-xxxx) Symbol Parameter I Read Current DDR I Read Current DDR3 I Program and Erase Current DDW I Standby Current SB I Input Leakage Current LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage ...
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... A Microchip Technology Company Table 15:AC Operating Characteristics (SST25VF080B-50-xx-xxxx) Symbo Serial Clock Frequency CLK T Serial Clock High Time SCKH T Serial Clock Low Time SCKL 4 T Serial Clock Rise Time (Slew SCKR Rate) T Serial Clock Fall Time (Slew SCKF Rate CE# Active Setup Time ...
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... A Microchip Technology Company Table 16:AC Operating Characteristics (SST25VF080B-80-xx-xxxx) Symbol 1 F Serial Clock Frequency CLK T Serial Clock High Time SCKH T Serial Clock Low Time SCKL 2 T Serial Clock Rise Time (Slew Rate) SCKR T Serial Clock Fall Time (Slew Rate) SCKF 3 T CE# Active Setup Time ...
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... Silicon Storage Technology, Inc. T CES SCKR DS DH MSB HIGH-Z T SCKL T SCKH CLZ MSB HHH HLS Mbit SPI Serial Flash SST25VF080B Data Sheet T CPH CEH CHS SCKF LSB HIGH-Z T CHZ LSB 1296 SerOut.0 T HHS T HLH T LZ S71296-05-000 1296 SerIn.0 1296 Hold.0 02/11 ...
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... PU-READ T PU-WRITE V HT INPUT REFERENCE POINTS V LT (0.9V ) for a logic “1” and V IHT DD 90%) are <5 ns Mbit SPI Serial Flash SST25VF080B Device fully accessible 1296 PwrUp OUTPUT V LT 1296 IORef.0 (0.1V ) for a logic “0”. Measure- ILT DD (0.6V ) and V (0.4V ) ...
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... A Microchip Technology Company Figure 27:A Test Load Example ©2011 Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash TO TESTER TO DUT 1296 TstLd.0 29 SST25VF080B Data Sheet C L S71296-05-000 02/11 ...
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... S2AE XXXX - XXXX 30 8 Mbit SPI Serial Flash SST25VF080B Data Sheet Environmental Attribute non-Pb / non-Sn contact (lead) finish non-Pb / non-Sn contact (lead) finish: Nickel plating with Gold top (outer) layer Package Modifier leads or contacts Package Type S = SOIC 150 mil body width ...
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... SST25VF080B-50-4C-S2AF SST25VF080B-50-4I-S2AF SST25VF080B-80-4C-S2AE SST25VF080B-80-4I-S2AE SST25VF080B-80-4C-SAE SST25VF080B-80-4I-SAE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales rep- resentative to confirm availability of valid combinations and to determine availability of new combinations. ©2011 Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash ...
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... SST Package Code: S2A ©2011 Silicon Storage Technology, Inc. TOP VIEW SIDE VIEW 5.40 5.15 2.16 8.10 1.75 7.70 0.25 0. Mbit SPI Serial Flash SST25VF080B Data Sheet 0.50 0.35 1.27 BSC 0.25 END VIEW 0.05 08-soic-EIAJ-S2A-3 1mm S71296-05-000 0° 8° 0.80 ...
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... SST Package Code: SA ©2011 Silicon Storage Technology, Inc. SIDE VIEW TOP VIEW 1.27 BSC 0.25 0.10 4.00 3.80 1.75 6.20 1.35 5. Mbit SPI Serial Flash SST25VF080B Data Sheet 7° 4 places 0.51 0.33 END VIEW 45° 4 places 0.25 0.19 1.27 0.40 08-soic-5x6-SA-8 1mm S71296-05-000 7° ...
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... Silicon Storage Technology, Inc. TOP VIEW SIDE VIEW 5.00 0 .10 6.00 0.10 0.80 0.70 leads the unit Mbit SPI Serial Flash SST25VF080B BOTTOM VIEW 0.2 4.0 0.076 3.4 0.05 Max CROSS SECTION 1mm 8-wson-5x6-QA-9.0 S71296-05-000 Data Sheet Pin #1 1.27 BSC ...
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... SST Package Code: PA ©2011 Silicon Storage Technology, Inc. TOP VIEW 0.355 0.400 0.245 0.260 SIDE VIEW 0.126 0.142 0.015 min 0.100 BSC 35 8 Mbit SPI Serial Flash SST25VF080B Data Sheet END VIEW 0.300 0.325 0.335 0.375 0.25 inches 8-pdip-PA-1.0 S71296-05-000 0.008 0.014 02/11 ...
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... Edited “Read (25/33 MHz)” on page 10 and “High-Speed-Read (66/80 MHz)” on page 11. Added Table 11 on page 24 and Table 16 on page 26 Edited Product Ordering Information Added Valid Combinations SST25VF080B-80-4C-S2AE, SST25VF080B-80-4I-S2AE, SST25VF080B-80-4C-QAE, and SST25VF080B-80-4I-QAE Updated “Auto Address Increment (AAI) Word-Program”, “End-of-Write Detection”, and “Hardware End-of-Write Detection” on page 13. ...