STM8AF52AATCY STMicroelectronics, STM8AF52AATCY Datasheet - Page 25
STM8AF52AATCY
Manufacturer Part Number
STM8AF52AATCY
Description
8 BITS MICROCONTR
Manufacturer
STMicroelectronics
Series
STM8Ar
Datasheet
1.STM8AF5289TCY.pdf
(106 pages)
Specifications of STM8AF52AATCY
Core Processor
STM8A
Core Size
8-Bit
Speed
24MHz
Connectivity
CAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8AF52AATCY
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM8AF52/62xx, STM8AF51/61xx
5.9.3
5.9.4
Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
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Inter integrated circuit (I
The devices covered by this datasheet contain one I
on all the supported packages.
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Maximum speed: 8 Mbit/s or f
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave mode/master mode management by hardware or software for both master and
slave
Programmable clock polarity and phase
Programmable data order with MSB-first or LSB-first shifting
Dedicated transmission and reception flags with interrupt capability
SPI bus busy status flag
Hardware CRC feature for reliable communication:
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–
I
–
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I
–
–
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
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–
Status flags:
–
–
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Error flags:
–
–
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2
2
C master features:
C slave features:
CRC value can be transmitted as last byte in Tx mode
CRC error checking for last received byte
Clock generation
Start and stop generation
Programmable I
Stop bit detection
Standard speed (up to 100 kHz),
Fast speed (up to 400 kHz)
Transmitter/receiver mode flag
End-of-byte transmission flag
I
Arbitration lost condition for master mode
Acknowledgement failure after address/data transmission
Detection of misplaced start or stop condition
Overrun/underrun if clock stretching is disabled
2
C busy flag
2
C address detection
Doc ID 14395 Rev 8
2
C) interface
MASTER
/2 both for master and slave
2
C interface. The interface is available
Product overview
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