STM8AF6268TDX STMicroelectronics, STM8AF6268TDX Datasheet - Page 89

• Manufacturer Part Number: STM8AF6268TDX
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8Ar

Specifications of STM8AF6268TDX

• Core Processor: STM8A
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 32-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM8AF61xx, STM8AF62xx
Table 52.
31-Jan-2011
Date
Document revision history (continued)
Revision
5
Modified references to reference manual, and Flash programming
manual in the whole document.
Added reference to AEC Q100 standard on cover page.
Renamed timer types as follows:
– Auto-reload timer to general purpose timer
– Multipurpose timer to advanced control timer
– System timer to basic timer
Introduced concept of medium density Flash program memory.
Updated timer names in
Added TMU brief description in
EEPROM, and updated TMU_MAXATT description in
Option byte
Updated clock sources in clock controller features
Changed 16MHZTRIM0 to HSITRIM bit in
Added
Updated
Added calibration using TIM3 in
Added
naming
Added
converter
microcontroller pin
Updated SPI data rate to 10 Mbit/s or f
Serial peripheral interface
Added reset state in
Table 10: STM8AF61xx/62xx (32 Kbytes) microcontroller pin
description: added
corrected wpu input for PE1 and PE2, and renamed TIMn_CCx and
TIMn_NCCx to TIMn_CHx and TIMn_CHxN, respectively.
Section 7.2: Register
Replaced tables describing register maps and reset values for non-
volatile memory, global configuration, reset status, clock controller,
interrupt controller, timers, communication interfaces, and ADC, by
Table 13: General hardware register
Added
register
Added SWIM and debug module register map.
Doc ID 14952 Rev 5
Table 7: ADC naming
Table 4: Peripheral clock gating bits
Note 1
Note 1
correspondence.
map. Updated register reset values for Px_IDR registers.
Section 5.6: Low-power operating
(ADC)and
description.
related AIN12 pin in
for Px_IDR registers in
description.
Note 7
Table 10: STM8AF61xx/62xx (32 Kbytes)
Table 9:
map:
Figure 1: STM8A block
(SPI).
related to PD1/SWIM, modified
and
Legend/abbreviation.
Changes
Section 5.4: Flash program and data
Section 5.7.2: Auto-wakeup
Table 8: Communication peripheral
Section 5.8: Analog-to-digital
map.
Table 12: I/O port hardware
MASTER
Section : User
in
modes.
Section
/2 in
diagram.
Revision history
(Section
Section 5.9.1:
5.5.6.
Table 18:
trimming.
Note
5.5.1).
counter.
6,
89/91