SC16C650BIA44 NXP Semiconductors, SC16C650BIA44 Datasheet - Page 16

• Manufacturer Part Number: SC16C650BIA44
• Manufacturer: NXP Semiconductors

Specifications of SC16C650BIA44

• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
7. Register descriptions
Table 8.
[1]
[2]
[3]
[4]
[5]
SC16C650B_4
Product data sheet
A2 A1 A0 Register Default
General register set
0
0
0
0
0
0
1
1
1
1
Special register set
0
0
Enhanced register set
0
1
1
1
1
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
These bits are only accessible when EFR[4] is set.
This function is not supported in the HVQFN32 package, and should not be written.
OUT2 pin is not supported in the HVQFN32 package, and this bit should not be written.
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
SC16C650B internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
EFR
Xon1
Xon2
Xoff1
Xoff2
[7]
[2]
[8]
Table 8
The assigned bit functions are more fully defined in
[1]
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
00
00
00
00
00
details the assigned bit functions for the seventeen SC16C650B internal registers.
Bit 7
bit 7
bit 7
CTS
interrupt
[3]
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
Clock
select
FIFO
data
error
DCD
bit 7
bit 7
bit 15
Auto
CTS
bit 7
bit 15
bit 7
bit 15
[3]
Bit 6
bit 6
bit 6
RTS
interrupt
[3]
RCVR
trigger
(LSB)
FIFOs
enabled
set
break
IR
enable
trans.
empty
RI
bit 6
bit 6
bit 14
Auto
RTS
bit 6
bit 14
bit 6
bit 14
Rev. 04 — 14 September 2009
[3]
Bit 5
bit 5
bit 5
Xoff
interrupt
[3]
TX
trigger
(MSB)
INT
priority
bit 4
set parity even
INT type
select
trans.
holding
empty
DSR
bit 5
bit 5
bit 13
Special
char.
select
bit 5
bit 13
bit 5
bit 13
UART with 32-byte FIFOs and IrDA encoder/decoder
[3]
[3]
Bit 4
bit 4
bit 4
Sleep
mode
TX
trigger
(LSB)
INT
priority
bit 3
parity
loopback
break
interrupt
CTS
bit 4
bit 4
bit 12
Enable
IER[4:7],
ISR[4,5],
FCR[4,5],
MCR[5:7]
bit 4
bit 12
bit 4
bit 12
[3]
[3]
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA mode
select
INT priority
bit 2
parity
enable
OUT2
framing
error
bit 3
bit 3
bit 11
Cont-3
Tx, Rx
control
bit 3
bit 11
bit 3
bit 11
DCD
Section 7.1
[4]
[5]
Bit 2
receive
line status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits
OUT1,
OUT
parity
error
Cont-2
Tx, Rx
control
bit 2
bit 2
bit 2
bit 2
bit 10
bit 2
bit 10
bit 2
bit 10
RI
through
SC16C650B
[6]
© NXP B.V. 2009. All rights reserved.
Section
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
Cont-1
Tx, Rx
control
bit 1
bit 9
bit 1
bit 9
DSR
7.11.
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
Cont-0
Tx, Rx
control
bit 0
bit 8
bit 0
bit 8
CTS
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