ISP1504CBSTM STEricsson, ISP1504CBSTM Datasheet - Page 80

• Manufacturer Part Number: ISP1504CBSTM
• Manufacturer: STEricsson

Specifications of ISP1504CBSTM

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 12. LINESTATE[1:0] encoding for upstream
Table 13. LINESTATE[1:0] encoding for downstream
Table 14. Encoded V
Table 15. V
Table 16. Encoded USB event signals . . . . . . . . . . . . . .30
Table 17. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .34
Table 18. Link decision times . . . . . . . . . . . . . . . . . . . . .35
Table 19. Immediate register set overview . . . . . . . . . . .47
Table 20. Extended register set overview . . . . . . . . . . . .47
Table 21. Vendor ID Low register (address R = 00h)
Table 22. Vendor ID High register (address R = 01h)
Table 23. Product ID Low register (address R = 02h)
Table 24. Product ID High register (address R = 03h)
Table 25. Function Control register (address R =
Table 26. Function Control register (address R =
Table 27. Interface Control register (address R =
Table 28. Interface Control register (address R =
Table 29. OTG Control register (address R = 0Ah to
Table 30. OTG Control register (address R = 0Ah to
Table 31. USB Interrupt Enable Rising Edge register
Table 32. USB Interrupt Enable Rising Edge register
ISP1504A_ISP1504C_3
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 6-pin serial mode . . . . . . .17
Signal mapping for 3-pin serial mode . . . . . . .18
Operating states and their corresponding
resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18
OTG Control register power control bits . . . . .25
facing ports: peripheral . . . . . . . . . . . . . . . . . .27
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .28
typical applications . . . . . . . . . . . . . . . . . . . . . .29
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
04h to 06h, W = 04h, S = 05h, C = 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
04h to 06h, W = 04h, S = 05h, C = 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
07h to 09h, W = 07h, S = 08h, C = 09h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
07h to 09h, W = 07h, S = 08h, C = 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .52
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit description . . . . . . . . . . . . . . . . . .52
BUS
indicators in RXCMD required for
BUS
voltage state . . . . . . . . . . . . . .28
Rev. 03 — 7 April 2008
Table 33. USB Interrupt Enable Falling Edge register
Table 34. USB Interrupt Enable Falling Edge register
Table 35. USB Interrupt Status register (address
Table 36. USB Interrupt Status register (address
Table 37. USB Interrupt Latch register (address
Table 38. USB Interrupt Latch register (address
Table 39. Debug register (address R = 15h) bit
Table 40. Debug register (address R = 15h) bit
Table 41. Scratch register (address R = 16h to 18h,
Table 42. Power Control register (address R = 3Dh to
Table 43. Power Control register (address R = 3Dh to
Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. Recommended operating conditions . . . . . . . . 57
Table 46. Static characteristics: supply pins . . . . . . . . . . 58
Table 47. Static characteristics: digital pins . . . . . . . . . . 58
Table 48. Static characteristics: digital pin FAULT . . . . . 59
Table 49. Static characteristics: digital pin PSW_N . . . . 59
Table 50. Static characteristics: analog I/O pins (DP,
Table 51. Static characteristics: charge pump . . . . . . . . 61
Table 52. Static characteristics: V
Table 53. Static characteristics: V
Table 54. Static characteristics: ID detection circuit . . . . 62
Table 55. Static characteristics: resistor reference . . . . . 62
Table 56. Dynamic characteristics: reset and clock . . . . 64
Table 57. Dynamic characteristics: digital I/O pins . . . . . 65
Table 58. Dynamic characteristics: analog I/O pins (DP
Table 59. Recommended bill of materials . . . . . . . . . . . . 68
Table 60. SnPb eutectic process (from J-STD-020C) . . . 74
Table 61. Lead-free process (from J-STD-020C) . . . . . . 74
Table 62. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 63. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 77
(address R = 10h to 12h, W = 10h, S = 11h,
C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 52
(address R = 10h to 12h, W = 10h, S = 11h,
C = 12h) bit description . . . . . . . . . . . . . . . . . . 52
R = 13h) bit allocation . . . . . . . . . . . . . . . . . . . 53
R = 13h) bit description . . . . . . . . . . . . . . . . . . 53
R = 14h) bit allocation . . . . . . . . . . . . . . . . . . . 53
R = 14h) bit description . . . . . . . . . . . . . . . . . . 54
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
W = 16h, S = 17h, C = 18h) bit description . . . 54
3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
and DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ISP1504A; ISP1504C
ULPI HS USB OTG transceiver
BUS
BUS
comparators . . . . 61
resistors . . . . . . . . 62
© NXP B.V. 2008. All rights reserved.
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