ISP1507ABSTM STEricsson, ISP1507ABSTM Datasheet
ISP1507ABSTM
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ISP1507ABSTM Summary of contents
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ISP1507A; ISP1507B ULPI Hi-Speed USB On-The-Go transceiver Rev. 04 — 20 May 2010 1. General description The ISP1507 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement ...
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Integrated 5 V charge pump; also supports external charge pump switch Complete control over bus resistors Data line and V Integrated V Integrated cable (ID) detector Highly optimized ULPI-compliant 60 MHz, 12-bit interface between the core ...
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... Set-Top Box (STB) Video camera 4. Ordering information Table 1. Ordering information Commercial Marking Crystal or clock product code frequency [1] ISP1507ABSTM 507A 19.2 MHz [1] ISP1507BBSTM 507B 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. CD00222689 Product data sheet ISP1507A ...
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Block diagram 27 CLOCK 26, 8 28, 31, 32 DATA [7:0] ULPI INTERFACE 19 DIR 20 STP 21 NXT 29 CHIP_SELECT_N 17 RESET_N GLOBAL CLOCKS 15 XTAL1 16 XTAL2 2, 22, 30 interface voltage V CC(I/O) ...
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Pinning information 6.1 Pinning Fig 2. Pin configuration HVQFN32; top view 6.2 Pin description Table 2. [1][2] Symbol DATA0 V CC(I/O) RREF DM DP FAULT ID CPGND C_B CD00222689 Product data sheet terminal 1 index area DATA0 1 V ...
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Table 2. [1][2] Symbol C_A V CC PSW_N V BUS REG3V3 XTAL1 XTAL2 RESET_N REG1V8 DIR STP NXT V CC(I/O) DATA7 DATA6 DATA5 DATA4 CLOCK DATA3 CD00222689 Product data sheet Pin description …continued [3] Pin Type Description 10 AI/O flying ...
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Table 2. [1][2] Symbol CHIP_SELECT_N 29 V CC(I/O) DATA2 DATA1 GND [1] Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals. [2] For details on external components required on each pin, see list of materials and ...
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Functional description 7.1 ULPI interface controller The ISP1507 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to the USB link. The ULPI interface controller provides the ...
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Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed • Squelch circuit to detect high-speed bus activity • High-speed disconnect detector 45 Ω high-speed bus terminations on DP and DM for peripheral and host modes • ...
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Resistors to temporarily charge and discharge V • Charge pump to provide 5 V power on V power from the ISP1507 V 7.6.1 ID detector The ID detector detects which end of the micro-USB cable is plugged in. The ...
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Charge pump The ISP1507 uses a built-in charge pump to supply current The charge pump works as a capacitive DC-DC converter. An external holding capacitor, C which also shows a typical OTG V amount ...
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V CC(I/O) The input power pin that sets the I/O voltage level. For details, see and Section • CHIP_SELECT_N • CLOCK • DATA[7:0] • DIR • NXT • RESET_N • STP 7.9.3 RREF Resistor reference analog I/O pin. A ...
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C_A and C_B The C_A and C_B pins are to connect the flying capacitor of the charge pump. The output current capability of the charge pump depends on the value of the capacitor used, as shown in Table For ...
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The V BUS To prevent electrical overstress strongly recommended that you attach a series resistor on the V internal charge pump. For details, see 7.9.12 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ...
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STP ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link can optionally assert STP to abort the ISP1507, causing ...
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Modes of operation 8.1 ULPI modes The ISP1507 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will ...
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Table 4. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1507 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in ...
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Table 5. Signal mapping during low-power mode Signal Maps to Direction Reserved DATA2 O INT DATA3 O Reserved DATA[7:4] O 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed ...
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Table 7. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.2 USB and OTG state transitions A Hi-Speed USB peripheral, host or OTG device handles more than one electrical ...
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Table 8. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] Host low-speed 10b 1b suspend Host low-speed 10b 1b resume Host Test J or Test K 00b 0b Peripheral settings Peripheral chirp ...
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Protocol description The following subsections describe the protocol for using the ISP1507. 9.1 ULPI references The ISP1507 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin Interface (ULPI) ...
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If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 6. The recommended ...
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CC(I/O) REG1V8 t REGUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1507. The ISP1507 regulator starts to turn on. CC CC(I/O) t2 ...
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The interface protect feature prevents unwanted activity of the ISP1507 whenever the ULPI interface is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1507. The interface protect feature can be disabled ...
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The ULPI controller is forced into an idle state and any ULPI command is ignored. entering 3-state mode CLOCK CHIP_ SELECT_N DATA[7:0] DIR NXT STP Fig 8. Entering and exiting 3-state in normal mode CLOCK CHIP_ SELECT_N DATA[7:0] TXCMD ...
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V power and fault detection BUS 9.4.1 Driving The ISP1507 provides a built-in charge pump. To enable the charge pump, the link must set the DRV_VBUS bit in the OTG_CTRL register (see The ISP1507 also ...
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Table 10. TXCMD byte format Command Command code Command payload type name DATA[7:6] DATA[5:0] Idle 00b 00 0000b Packet 01b 00 0000b transmit 00 XXXXb Register 10b 10 1111b write XX XXXXb Register read 11b 10 1111b XX XXXXb 9.5.2 ...
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CLOCK turnaround DATA [ 7:0 ] DIR STP NXT Fig 10. Single and back-to-back RXCMDs from the ISP1507 to the link 9.5.2.1 Linestate encoding LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1507 detects a change in ...
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Table 13. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. ...
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USE_EXT_VBUS_IND, IND_PASSTHRU Fig 11. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers. The link ...
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OTG devices: provide a minimum then there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 ...
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Register read and write operations Figure 12 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1507 unexpectedly asserts DIR during the operation. When a register ...
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T up its clock within 5.6 ms, leaving 200 μs for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow ...
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USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR STP NXT ...
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USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. link sends TXCMD CLOCK DATA[7:0] TXCMD DIR STP NXT Fig 14. Example ...
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Allowed link decision time The amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in values given in packet sequences and timing are shown in UTMI+ Low ...
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DP or DATA DM CLOCK D D N−1 N DATA [7:0] DIR STP NXT TX end delay (two to five clocks) Fig 15. High-speed transmit-to-transmit packet timing DP or EOP DATA DM CLOCK N−4 N−2 DATA ...
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ISP1507 operates just as in full-speed mode, and sends all data with the full-speed rise time and fall time. Whenever the link transmits a USB packet in preamble mode, the ISP1507 will automatically send a preamble header ...
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Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to 10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on LINESTATE, and asserts STP to wake ...
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DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 18. Full-speed suspend and resume ...
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The sequence of events related to a host and a peripheral, both with ISP1507 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN ...
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HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP ...
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Remote wake-up The ISP1507 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols ...
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LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 20. Remote wake-up from ...
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PHY will not transmit any EOP. The ISP1507 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must ...
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OTG charge pump A description of the charge pump is given in configured as an A-device, it can provide the V Control of the charge pump is described in 9.12.2 OTG comparators The ISP1507 provides comparators that conform to ...
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SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 22. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 23. ...
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Aborting transfers The ISP1507 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 9.15 Avoiding contention on the ULPI data bus Because the ULPI data bus is ...
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Register map Table 19. Immediate register set overview Field name Size (bit) VENDOR_ID_LOW 8 VENDOR_ID_HIGH 8 PRODUCT_ID_LOW 8 PRODUCT_ID_HIGH 8 FUNC_CTRL 8 INTF_CTRL 8 OTG_CTRL 8 USB_INTR_EN_R_E 8 USB_INTR_EN_F_E 8 USB_INTR_STAT 8 USB_INTR_L 8 DEBUG 8 SCRATCH 8 Reserved ...
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Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 VENDOR_ID_LOW register Table 21 shows the bit description of the register. Table 21. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Legend: * reset ...
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Table 26. FUNC_CTRL - Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the ...
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Table 28. INTF_CTRL - Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1507 to protect ...
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Table 29. OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 6 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 0 Access R/W/S/C R/W/S/C Table 30. ...
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USB_INTR_EN_R_E register The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all transitions are enabled. Table 31. USB_INTR_EN_R_E - ...
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Table 34. USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit description Bit Symbol Description 2 SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for ...
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Table 38. USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description Bit Symbol Description reserved 4 ID_GND_L ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared when this register ...
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Vendor-specific registers Addresses 30h to 3Fh contain vendor-specific registers. 10.1.14 PWR_CTRL register This register controls various aspects of the ISP1507. See Table 42. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh 3Dh ...
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ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, ID, V minimum of ±4 kV ESD protection. Capacitors 0.1 μF and 1 μF must be connected in parallel from V Remark: ...
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Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current ...
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Static characteristics Table 46. Static characteristics: supply pins CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V ...
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Table 47. Static characteristics: digital pins Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N and CHIP_SELECT_N; unless otherwise specified CC(I/O) Typical values are at ...
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Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V ...
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Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter Resistance ...
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Table 53. Static characteristics CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter R pull-up resistance on pin ...
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I CC(cp) (mA) 100 = denotes charge pump supply current. CC(cp) Fig 25. Charge pump supply current as a function of ...
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Dynamic characteristics Table 56. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
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Table 57. Dynamic characteristics: digital I/O pins − ° 3 3 +85 CC amb Symbol Parameter 1.95 V CC(I/O) t DATA set-up time with respect ...
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Table 58. Dynamic characteristics: analog I/O pins (DP and CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
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HSR Fig 29. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL ...
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Application information Table 59. Recommended list of materials [1] Designator Application C highly recommended for all bypass applications C charge pump is used cp(C_A)-(C_B) C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host ...
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C bypass V BUS 1 D− USB GND 5 MICRO-AB RECEPTACLE SHIELD 6 SHIELD 7 8 SHIELD SHIELD 9 C VBUS C bypass (1) Frequency is version ...
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V IN FAULT R pullup V BUS SWITCH OUT ON V BUS 1 D− USB 3 STANDARD-A RECEPTACLE GND 4 C VBUS SHIELD 5 SHIELD 6 f i(XTAL1) (1) ...
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C bypass R VBUS V 1 BUS D− USB STANDARD-B GND RECEPTACLE 4 SHIELD 5 SHIELD 6 C VBUS C bypass (1) Frequency is version dependent: ISP1507A: 19.2 MHz; ...
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Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS ...
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Abbreviations Table 60. Acronym ASIC ATX CD-RW EOP ESD ESR FS HBM HNP HS ID IEC LS NRZI OTG PCB PHY PID PLD PLL POR RXCMD SE0 SOF SRP SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ [1] Physical ...
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References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specification Rev. 1.0 [5] USB 2.0 Transceiver Macrocell Interface (UTMI) ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN32; top ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 Immediate register set . . . . . . ...
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... Product data sheet Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 04 — 20 May 2010 ISP1507A; ISP1507B ULPI HS USB OTG transceiver © ...