ISP1507CBS STEricsson, ISP1507CBS Datasheet - Page 24

• Manufacturer Part Number: ISP1507CBS
• Manufacturer: STEricsson

Specifications of ISP1507CBS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 9.
ISP1507C_ISP1507D_1
Product data sheet
DATA
1 to 0
3 to 2
5 to 4
6
7
Fig 6.
Name
LINESTATE
V
RxEvent
reserved
ALT_INT
DATA [ 7:0 ]
BUS
Single and back-to-back RXCMDs from the ISP1507 to the link
CLOCK
RXCMD byte format
NXT
STP
DIR
state
9.5.2.1 Linestate encoding
Description and value
LINESTATE signals: For a definition of LINESTATE, see
DATA0 — LINESTATE[0]
DATA1 — LINESTATE[1]
Encoded V
Encoded USB event signals: For an explanation of RxEvent, see
-
By default, this signal is not used and is not needed in typical designs. Optionally, the link can enable
the BVALID_RISE and/or BVALID_FALL bits in the PWR_CTRL register (see
Corresponding changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit
asserted.
LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1507 detects
a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]
value. The value given on LINESTATE[1:0] depends on the setting of various registers.
Table 10
peripherals.
which applies to host controllers. Dual-role devices must choose the correct table,
depending on whether it is in peripheral or host mode.
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BUS
shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to
voltage state: For an explanation of the V
Table 11
Single RXCMD
RXCMD
shows the LINESTATE[1:0] encoding for downstream facing ports,
Rev. 01 — 28 May 2008
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ULPI HS USB host and peripheral transceiver
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ISP1507C; ISP1507D
Section
BUS
Back-to-back RXCMDs
state, see
RXCMD
9.5.2.1.
Section
RXCMD
Section
9.5.2.4.
Section
9.5.2.2.
© NXP B.V. 2008. All rights reserved.
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004aaa695
10.1.14).
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