ISP1505ABS,518 NXP Semiconductors, ISP1505ABS,518 Datasheet - Page 32
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ISP1505ABS,518
Manufacturer Part Number
ISP1505ABS,518
Description
RF Transceiver USB ULPI TRANSCEIVER
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1505ABS557.pdf
(76 pages)
Specifications of ISP1505ABS,518
Number Of Transceivers
1
Esd Protection
YeskV
Operating Supply Voltage (typ)
Not RequiredV
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
Not RequiredV
Operating Supply Voltage (min)
Not RequiredV
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Supply Voltage
1.65 V to 3.6 V
Mounting Style
SMD/SMT
Package / Case
HVQFN-24
Lead Free Status / RoHS Status
Compliant
Other names
935278318518 ISP1505ABS-T
NXP Semiconductors
Table 16.
ISP1505A_ISP1505C_3
Product data sheet
Packet sequence High-speed
Transmit-Transmit
(host only)
Receive-Transmit
(host or
peripheral)
Receive-Receive
(peripheral only)
Transmit-Receive
(host or
peripheral)
Fig 11. High-speed transmit-to-transmit packet timing
CLOCK
DATA
DP or
DIR
[7:0]
STP
NXT
DM
D
N 1
Link decision times
D
N
link delay
15 to 24
1 to 14
1
92
DATA
TX end delay (two to five clocks)
Full-speed
link delay
7 to 18
7 to 18
1
80
EOP
Low-speed
link delay
77 to 247
77 to 247
1
718
Rev. 03 — 26 August 2008
link decision time (15 to 24 clocks)
USB interpacket delay (88 to 192 high-speed bit times)
Definition
Number of clock cycles a host link must wait before driving
the TXCMD for the second packet.
In high-speed, the link starts counting from the assertion of
STP for the first packet.
In full-speed, the link starts counting from the RXCMD,
indicating LINESTATE has changed from SE0 to J for the
first packet. The timing given ensures inter-packet delays of
2 bit times to 6.5 bit times.
Number of clock cycles the link must wait before driving the
TXCMD for the transmit packet.
In high-speed, the link starts counting from the end of the
receive packet; deassertion of DIR or an RXCMD, indicating
RxActive is LOW.
In full-speed or low-speed, the link starts counting from the
RXCMD, indicating LINESTATE has changed from SE0 to J
for the receive packet. The timing given ensures
inter-packet delays of 2 bit times to 6.5 bit times.
Minimum number of clock cycles between consecutive
receive packets. The link must be able to receive both
packets.
Host or peripheral transmits a packet and will time-out after
this number of clock cycles if a response is not received.
Any subsequent transmission can occur after this time.
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
IDLE
(one to two clocks)
© NXP B.V. 2008. All rights reserved.
TXCMD
TX start delay
004aaa712
SYNC
D0
31 of 75
D1