ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 41

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

Table 24.
ISP1705_2
Product data sheet
Packet sequence
Transmit-Transmit
(host only)
Receive-Transmit
(host or peripheral)
Receive-Receive
(peripheral only)
Transmit-Receive
(host or peripheral)
Fig 17. High-speed transmit-to-transmit packet timing
CLOCK
DATA
DP or
DIR
[7:0]
NXT
STP
DM
D
Link decision times
N 1
D
N
High-speed
link delay
15 to 24
1 to 14
1
92
DATA
TX end delay (two to five clocks)
Full-speed
link delay
7 to 18
7 to 18
1
80
EOP
Low-speed
link delay
77 to 247
77 to 247
1
718
Rev. 02 — 21 January 2009
link decision time (15 to 24 clocks)
USB interpacket delay (88 to 192 high-speed bit times)
Definition
Number of clock cycles a host link must wait before driving
the TXCMD for the second packet.
In high speed, the link starts counting from the assertion of
STP for the first packet.
In full speed, the link starts counting from the RXCMD,
indicating LINESTATE has changed from SE0 to J for the first
packet. The timing given ensures inter-packet delays of 2 bit
times to 6.5 bit times.
Number of clock cycles the link must wait before driving the
TXCMD for the transmit packet.
In high speed, the link starts counting from the end of the
receive packet; deassertion of DIR or an RXCMD indicating
RxActive is LOW.
In full speed or low speed, the link starts counting from the
RXCMD, indicating LINESTATE has changed from SE0 to J
for the receive packet. The timing given ensures inter-packet
delays of 2 bit times to 6.5 bit times.
Minimum number of clock cycles between consecutive
receive packets. The link must be capable of receiving both
packets.
Host or peripheral transmits a packet and will time-out after
this number of clock cycles if a response is not received. Any
subsequent transmission can occur after this time.
IDLE
ULPI Hi-Speed USB transceiver
© ST-NXP Wireless 2009. All rights reserved.
(one to two clocks)
TXCMD
TX start delay
ISP1705
SYNC
004aaa712
D0
40 of 89
D1